AN-02 — Importing a Gerber file set, and turning it into a schematic
A fabricator's Gerber and drill files brought into circuitRF as an editable board, its stackup checked, and its copper read back as a schematic that simulates without an EM run — walked through on the shipped Artwork to Schematic example.
The board
A small two-layer board, as a fabricator receives it. A 450 µm microstrip line enters at the left edge, turns up
through a 90° bend, passes a tee whose branch is an open stub, then a series 2.2 pF capacitor C1, a shunt inductor
L1 to a ground via, and a series 10 Ω resistor R1, and leaves at the top edge. The bottom layer is a solid ground
plane under a 254 µm laminate.
File ▸ New ▸ Examples ▸ Artwork to Schematic gives you a copy. Its fab folder holds what left the design office:
File
What it is
fab/Board/Board.GTL
Top copper: the line, the stub and the parts' pads
fab/Board/Board.GBL
Bottom copper: the ground plane
fab/Board/Board.GTS
Top solder mask: an opening over each pad
fab/Board/Board.drl
Excellon drill file: one 0.3 mm hole, the via
fab/Board/Board.gbrjob
Job file: names the three Gerber files and what each one is. It states no stackup.
fab/Board.pos
Placement file: where C1, L1 and R1 sit and how they are turned
fab/Board-bom.csv
Bill of materials: C1, L1 and R1. L1's row has no value, on purpose — a real BOM is often incomplete.
The workspace also holds Board, which is this same file set already imported with its stackup corrected, and
Board design, the schematic the board was drawn from. Keep Board design closed until
the end: it is the answer to compare against.
Every count, thickness and decibel on this page came out of a run on this example: the import and the recognition
the figures were captured from, and the command-line runs quoted in the last section.
Pointing at the files
File ▸ Import ▸ Gerber… opens a file picker. Point it at a folder and you get the whole board. Pick one
file and circuitRF asks whether the folder was what you meant, and says what else is in it. Pick Board.GTL
alone and this is the question:
Board.GTL picked on its own. The question says what the folder holds besides it, counted by content, and Whole Folder is the default.
One Gerber file is one layer, with no drill data, no other copper and no outline, which is occasionally what you
want and usually is not. Whole Folder is the default. Another Folder… opens the folder picker instead, and
Cancel creates nothing.
The counts in that question are made by content, never by extension: every file is opened and classified, by
the same classifier the import itself uses. A file in the folder that is neither artwork nor drill data is
skipped, and the summary names it, so a folder with other things in it is safe to point at. This one holds
nothing else.
Which layer is which
Each artwork file's identity comes from the strongest source the set offers, in this order:
the job file (.gbrjob), which settles which files belong to the board and what each one is, and can
carry the stackup;
the file's own X2 attributes (%TF.FileFunction), which also give a copper layer's position in the stack;
a Gerber suffix in your workspace technology that matches the file's extension;
a name heuristic — copper top, bottom, inner or numbered from the top (MET-1 … MET-4,
Signal_01 … Signal_03), mask, silk, paste, outline, drill, including the short spellings (TOP-COP,
BTM-COP, TOP-SLD, SLK, SM, SP_Top, HOLE, PCB FRAME). A Gerber file of the vias (Via_1_2_3)
is a drill layer, and the numbers after "via" are the copper layers it joins. A silkscreen or mask whose
name gives no side is taken as the top one;
the layer-mapping dialog, for anything still unnamed. Mapping an unnamed file onto a copper layer of the
technology makes it that conductor in the stackup.
This board's job file names all three Gerber files, so the first rung settles every one of them. The files carry
X2 attributes as well, but the job file is asked first. The import summary says so, file by file:
Board.GBL → Bottom (declared by the job file): 1 flash(es), 0 stroke(s), 1 region(s).
Board.GTL → Top (declared by the job file): 2 flash(es), 0 stroke(s), 16 region(s).
Board.GTS → Soldermask Top (declared by the job file): 0 flash(es), 0 stroke(s), 6 region(s).
Imported 3 artwork file(s) as 3 layer(s) and 26 shape(s): 3 layer(s) identified exactly,
0 guessed from the file name, 0 mapped by hand.
Read that last line on every import. "guessed from the file name" is the rung that can be confidently wrong:
a set with neither a job file nor X2 attributes lands there, and a name says what the person who chose it meant,
not what is in the file. The drill file is not in that count: Excellon is recognised
as drill data by what it contains, and is read separately.
The layer-mapping dialog and the Technology row
Every Gerber import opens the layer-mapping dialog. Its first row, Technology, decides which technology the
board lands in, and the table under it shows where each file goes in that technology.
The Layer Mapping dialog for the example's set. The workspace technology has two conductors, as the set has two copper files, so the Technology row opens on it, and every file is matched to one of its layers by name.
New technology from the files writes a technology for this import alone, beside the cell, built from what
the files say. Your workspace technology is read for layer names and never changed.
A technology you already have — any .ctech in the workspace, or a built-in one — is used: every file is
mapped onto that technology's own layers, nothing is added to it, nothing in it changes, and no .ctech is
written. A built-in technology is copied into tech/ when you press Continue. A file the technology has no
layer for (a paste stencil, say) keeps a layer of its own; the layout editor's
Layers list shows it after the technology's own layers, where it can be
hidden or locked like any other.
Changing the row re-proposes the table for that technology at once, without reading the files again. A
technology is offered only when its stackup has as many conductors as the set has copper files, counting the
files you mark as copper in the In the stackup as column described below. The others are listed with
their copper count and cannot be chosen until the count matches. The dialog opens on the workspace's default technology when
its count matches, and on New technology from the files otherwise. This workspace's default,
tech/board.ctech, has two conductors, as the set has two copper files, so the dialog opens on it, and all three
files are matched by name.
Use the technology you already have when it holds the fabricator's stackup. That is the usual case for a board
from your own design flow, and for any board built on a process you have set up once. Choose New when nothing
in the workspace describes this board, and then check what it guessed before you run anything on it.
The same row on a six-copper set, and its choices:
Import Gerber's Layer Mapping dialog for a six-copper set. The Technology row opens on the workspace's six-layer technology, and every file is matched to one of its layers by name. The layout will use that technology, and no technology is written.The Technology choices: a new technology from the files, every technology in the workspace, and the built-in ones, which are copied into tech/ when chosen. A technology whose copper count differs from the set's is listed but cannot be chosen.
An import into a chosen technology is refused, and creates nothing, when the set does not fit it:
the set has a different number of copper files than the technology has conductors;
a copper file lands on a conductor of a different rank — the file that says it is layer 2 on the technology's
third conductor;
two copper files land on one conductor;
plated drill data lands on a layer no via in that stackup binds. A drill file that only routes — the board
outline and its cutouts — or that says it is non-plated is not a via, and is kept as an unknown layer instead.
A file nothing could identify is asked where it goes in the stackup. Only a conductor enters the stackup, so
an unnamed file that is really a plane has to be told so, or it will be imported as drawing-only artwork and
nothing will treat it as copper. Its row gets an In the stackup as column: artwork, the default, copper
at a position in the copper order, or vias — a Gerber drawing of the plated holes, a flash per hole. A file
answered vias becomes a drill layer with a plated via entry in the stackup, through the whole board unless
its name states the copper layers it joins.
A made-up set with one file nothing identifies. Its row asks where it goes in the stackup: artwork, or copper at a position in the copper order.
The example board does not raise that question; the figure is a made-up set with one file that carries no
attribute and an extension no rung knows.
Drill data and vias
An Excellon file often does not say what its numbers mean. Units and zero suppression are inferred from the format
comment, the INCH/METRIC line, M71/M72, the tool diameters, and a cross-check of where the hits land
against the artwork's own extent. You are asked only when that inference had to guess, or when the cross-check
disagrees, and the question shows the evidence.
This board's drill file declares METRIC and writes every coordinate with a decimal point, so nothing is guessed
and nothing is asked:
Board.drl: mm 3:3 decimal-point coordinates. Units: millimetre — declared by the file (its INCH/METRIC line).
Digit format: not needed — every coordinate carries a literal decimal point. Zero suppression: not applicable —
every coordinate carries a literal decimal point.
A drill file that states none of that gets this, pre-filled with the inference:
The drill-format prompt on a made-up drill file that states neither its units nor its zero suppression: the inference, the evidence for it, and where the hits land against the artwork.
The made-up file behind that figure has one tool of 0.0118 and two hits, the first written X394Y591. The
inference reads the tool size as inches, defaults the digits to 2:4 with leading zeros suppressed, and then checks
the result against the artwork: both hits fall inside it. Correct whatever is wrong and press Import.
Cancel cancels the whole import — a board read at the wrong scale is worse than no board.
Vias are rebuilt wherever a drill hit and a copper flash share a coordinate: pad diameter, drill diameter,
barrel and landing layer, back to a real via. This board's one hole lands on its via pad:
Drill: 1 tool(s), 1 hit(s) → 1 via(s) (0 declared as vias by the files themselves), 0 unpaired hole(s),
0 component hole(s), 0 slot(s).
A hit with no flash under it stays a circle on the drill layer and is counted as unpaired; many of those
usually mean the artwork and the drill file are from different boards. Where the files declare a hole as a via or
a component hole (X2 ViaDrill / ComponentDrill) the declaration is used. These files do not, so the summary says
the via was rebuilt "without the file saying so": from artwork alone, a via and a plated component hole look the
same. What the via model needs from the stackup is in Vias.
Each drill file's layer span — which copper layers its holes join — is taken from the first of these that
states one, and the drill file's line in Messages names which:
the drill file's own FileFunction attribute (; #@! TF.FileFunction,Plated,1,2,Blind);
a board netlist (IPC-D-356) in the set, from the layer pair each blind or buried via record states;
the drill file's name, when it ends in a layer pair, as a set drilled by layer pair names its files
(board-1-2-laser.drl, board-3-8.drl).
The span sets the via's landing layer and the two ends of the drill layer's entry in the stackup. With none of
the three, the holes go through the whole board, and the line says so. This board's one drill file states no
span, and its holes do go through.
What you get
One flat cell, in a folder of its own at the top of the workspace, named after the folder the files were in.
This workspace already has a Board, so the import lands in Board_2: the cell Board_2, and with New,
the technology Board_2.ctech beside it. With a technology you chose instead, the layout references that file and
no technology is written.
The import's summary goes to the Messages panel, under the line that says
what was imported:
The Messages panel after the example's set is imported with New technology from the files: the result on the first row, and the import's summary under it.
Most of it is what the files said, file by file. Two paragraphs are not, and are written apart from the rest so
they can be found: the one beginning NOT STATED BY ANY FILE IN THIS SET lists every number the import made up,
and the plated-via paragraph names the wall thickness it defaulted. The last line is the one to take literally: a
whole board is not an EM problem. Crop the region you mean to simulate first, or read the board as a circuit,
below.
The cell opens in the layout editor:
The imported board in the layout editor, every layer shown: the bottom ground plane, the top copper, the solder mask openings and the via.
Cutting a region out of an imported board. Right-click the layout, choose
Crop to Rectangle… and drag a box around the part you mean to keep: a
connector and its feed, say. Every layer is cut to the box in one step, hidden and locked layers included, and
the board outline is redrawn to match. The confirmation lists each layer's counts first, and one undo puts the
whole board back.
Every shape that came in as a filled region is a polygon: Gerber has no rectangle, so a rectangle drawn in the
design that produced these files is a polygon here, and the summary counts them (23 on this board). The line
arrives as one polygon per stretch of copper, overlapping where the stretches meet:
The same board with only the top copper shown, zoomed on the bend, the tee and its open stub. The line arrives as one polygon per stretch of copper, overlapping where the stretches meet.
The round-trip table lists what survives an export and import and what
does not. On a board whose pours arrive as thousands of painted strokes, the Coalesce imported painted fill
into regions setting on the General page of Settings turns them back into the
regions they paint; it is on by default, and the summary names each layer it coalesced. With it off, the
summary's per-layer stroke counts show where a pour came in as strokes, and the layout editor's boolean
Union turns them into copper you can edit and mesh.
Check the stackup before you trust a number
No Gerber file states the substrate. The job file can, but this one does not, so under New the import
builds the stackup's structure from the files — two conductors, in the order the files declared, each bound to
its drawing layer — and fills in the rest with ordinary FR-4 so the board can be opened and looked at:
NOT STATED BY ANY FILE IN THIS SET, so circuitRF filled it in with ordinary FR-4 so the technology can be
simulated as it stands: copper thickness on 2 conductor(s) (35 um outer, 18 um inner); thickness on 1
dielectric(s) (1778 um each, sharing out a 1778 um board); relative permittivity 4.4 on 1 dielectric(s); loss
tangent 0.02 on 1 dielectric(s).
Open Board_2.ctech and its Stackup tab shows exactly that:
The Stackup tab of the technology the import wrote. The two conductors and their order come from the files; the copper thickness, the 1.778 mm FR-4 core, its permittivity and its loss tangent are the import's guess.
Every one of those numbers is wrong for this board. The fabricator's laminate is 254 µm, not 1.778 mm, with
εr3.66, not 4.4. On the guessed stackup the 450 µm line is a 115 Ω microstrip; on the
fabricator's it is 54 Ω (the MLIN model's static Z0, from the
line calculator on each technology).
The planes are guessed, and the summary says which. No file says which copper is a plane, so under New the
import marks as a ground reference every inner conductor whose copper covers at least half the board (the board
outline's area, or the box the copper spans when the set has none). The outer layers are left as signal layers,
because the parts and the ports are there, unless the board has no inner plane: then the outer conductor covering
most is the plane. Here that is the bottom conductor:
This conductor was marked as a ground reference, because its copper covers at least half of the box the copper
spans (the set has no board outline): 'Bottom Copper' (100%). An EM setup returns ports through a ground reference
and meshes its openings as drawn. To undo one, clear Ground reference on it in the Technology editor ▸ Stackup.
A power plane covering the board is marked the same way, which is right for EM: at RF it is a return path. The
stack's outer boundary follows the artwork too: when the bottom (or top) conductor carries artwork and is not a
ground reference, that boundary is set to Open, because a Ground boundary is a solid plane beyond the outer
copper that the board does not have. The summary names that change as well.
Type the fabricator's values in on the Stackup tab — the dielectric's thickness, εr and tan δ, the
copper thickness if it is not 35 µm — and check the ground references against the board. The example's
Board/Board.ctech is this same import with that done:
The example's Board.ctech in cross-section: the same import, with the fabricator's 254 um core and its permittivity of 3.66 typed in.
Under a technology you chose, nothing is guessed. The layout references tech/board.ctech and reads its stackup
— 254 µm, εr 3.66, the bottom conductor the ground reference — and the summary's closing line says which
file it used:
This import uses the technology 'round-trip' (tech/board.ctech): the layout references it, no technology was
written, and nothing in that one was changed.
When the set's job file does state a stackup and it differs from the technology you chose, the summary warns you
and says how they differ, layer by layer; the technology is used as it is, and the warning is the prompt to find
out which of the two is right.
From artwork to a schematic
The usual reason to import a board is to simulate it, and a whole board is too large for that as an EM problem:
the full-wave matrix grows as the square of the mesh, and a run whose matrix will not fit is refused before it
starts (what makes a run infeasible). But a board of ordinary SMT parts joined by
controlled-impedance lines is already a circuit, and Design ▸ Create ▸ Schematic from Artwork… reads it out of
the copper as one: lines, bends, tees, vias and parts, as native components that run as an ordinary S-parameter
simulation. The steps below run on the example's Board cell, whose stackup is already corrected.
1. Recognise. Open Board's layout and choose Design ▸ Create ▸ Schematic from Artwork…
(opening it). Recognition runs as the dialog opens. Give it the
placement file and the BOM: Placement…fab/Board.pos,
BOM…fab/Board-bom.csv.
Design > Create Schematic from Artwork on the shipped Artwork to Schematic example, with its placement file and bill of materials given: the options across the top, the parts table with every part the recognition read, and the report strip under it.
The report strip under the table says what was read: ground on the bottom plane, the via kept as a
VIAGND, two ports where the line leaves the board, seven
MLINs, a bend and a
tee, and one line end with nothing on it — the stub at (11550, 7450) µm.
The report says what each line of it means, and
what is recognised says what is not.
2. Review the parts table. C1 and R1 take their values from the BOM. L1's kind comes from the BOM's description and
its case from the land pattern, but nothing states its value, so it becomes the global variable L1_L,
starting at 1 µH — a shunt inductor large enough to be invisible, so the first simulation shows the lines alone.
Select a row and its pads are marked on the layout:
L1's row selected in Create Schematic from Artwork's parts table: its pads are marked on the layout, between the line and the via to ground.
The parts table lists every column and what you can correct in
each.
3. Create. Leave the target at New cell, Board_model,
and click Create. The schematic is written beside the artwork cell and opens:
Board_model as Create writes it: the lines, the bend and the tee read off the copper, the three parts, the via to ground, and a port where the line leaves each edge of the board.
Every line length came off the copper — 7.6 mm into the bend, 4 mm to the tee, a 3.5 mm stub, and so on to the
4.5 mm that leaves the top edge — and every one equals its line in Board design.
4. Simulate. Press Simulate. At 2 GHz Board_model reads S11 ≈ −7.7 dB. Simulate Board design:
−15.8 dB. Every value in the two schematics agrees except one, and the difference is L1.
5. Tune the unknown part. Open the Tuning panel on Board_model. L1_L is listed already, its range
100 nH to 10 µH. Click the minimum and type 1 nH, then drag the slider down
(a row of the Tuning panel). The match deepens as L1 falls, and at 8.2 nH —
the value in Board design — the two curves lie on top of each other: −15.8 dB at 2 GHz, and a minimum of −15.9 dB
just below it.
The Tuning panel on Board_model with L1_L's minimum lowered to 1 nH and the value at 8.2 nH.S11 of Board_model with L1 at its 1 uH starting value, of Board_model with L1 tuned to 8.2 nH, and of Board design (dashed), the schematic the board was drawn from.
Then, while you are here:
Show in Artwork, on the right-click menu of any component of Board_model, marks the copper it was read
from (Show in Artwork). On the stub's line:
Show in Artwork on the open stub's line in Board_model: the copper it was read from is marked on the layout.
Swap Line Type on one of the lines turns it into a TLIN, or a
CPWG, and back, keeping its width and length
(swapping a line type).
A schematic created this way keeps a record of the layout it came from; what that means when the layout changes
is in models existing artwork.
The same thing from the command line
Both halves have a command-line form, and both run the same import and the same
recognition as the GUI. From the example's workspace folder:
convert with a clay target is the Gerber import, writing into the folder you
name. With no workspace to open there is no default technology, so the import mints its own, as New does, and
says what it guessed on the same terms — here, from the run:
note: Board.gbrjob names 3 file(s) as part of this board.
note: Copper stack order was DECLARED for all 2 copper layer(s): Top Copper, Bottom Copper, top to bottom.
note: Board.drl: 1 tool(s), 1 hit(s) → 1 via(s). No layer span was declared — not by its FileFunction attribute or
its file name — so the holes are treated as through-hole.
note: NOT STATED BY ANY FILE IN THIS SET, so circuitRF filled it in with ordinary FR-4 so the technology can be
simulated as it stands: copper thickness on 2 conductor(s) (35 um outer, 18 um inner); thickness on 1
dielectric(s) (1778 um each, sharing out a 1778 um board); …
note: Imported 3 artwork file(s) as 3 layer(s) and 26 shape(s): 3 layer(s) identified exactly, 0 guessed from
the file name, 0 mapped by hand.
[circuitRF] wrote 1 cell(s) and a technology to imported/
The layers are called Top Copper and Bottom Copper here rather than Top and Bottom: in the GUI the
workspace technology lends its names to the New technology, and headless there is none to lend them.
--into-tech is the Technology row's other answer
(the technology, and why it matters here):
note: This import uses the technology 'round-trip' (../tech/board.ctech): the layout references it, no
technology was written, and nothing in that one was changed.
The path in that line is relative to the output folder, as it is relative to the workspace in the GUI.
recognize reads the board as Create Schematic from Artwork does and writes
nothing unless asked:
Ground is the largest copper on the reference conductor 'Bottom' at (14000, 23425) µm, and everything joined to it.
1 via to ground — a ground pad's or a shorted line's — kept as VIAGND.
2 ports where a line reaches the board edge: P1, P2.
3 parts were named by the placement file on land patterns found on the board: C1, L1, R1.
1 part has no known value and becomes a variable with a transparent starting value: L1_L.
9 line elements read from the traces: 7 MLIN, 1 MBEND, 1 MTEE.
7 segments read as microstrip (MLIN) under Auto (both side gaps within 3·H).
1 line ends on nothing a part, a via or a port lands on, and is left open (there is no open-end model): (11550, 7450) µm.
Refdes,Kind,Connection,Case,Value,Variable,Model,ModelFile,PartNumber,X,Y,Evidence,Confidence,Notes
C1,C,series,0402,2.2 pF,,Ideal,,,7825 µm,11350 µm,refdes=placement;kind=bom;case=land;value=bom,high,
L1,L,shunt,0402,,L1_L,Ideal,,,7425 µm,14025 µm,refdes=placement;kind=bom;case=land,high,
R1,R,series,0603,10 Ohm,,Ideal,,,7825 µm,17725 µm,refdes=placement;kind=bom;case=land;value=bom,high,
--into new:Board_model writes the schematic, as Create does. The parts table is the same CSV the dialog's
Export Parts… writes, so a table corrected in a spreadsheet goes back in with --parts
(from the command line).
Checklist
Check
Where it is reported
Every file you expected was imported, and none was skipped that should not have been
Import summary — the skipped files are named
No layer was guessed from the file name, or you have looked at each one that was
Import summary — the Imported N artwork file(s) line
The drill data agrees with the artwork, and the via count is what the board has
Import summary — the Drill: line; unpaired should be 0
The technology is the one holding the fabricator's stackup, or you chose New knowing it guesses
The Technology row; the summary's closing line
Under New: every number in the NOT STATED paragraph replaced with the fabricator's
The Stackup tab
The conductors marked as ground references are the board's planes
The import summary's marked as a ground reference line; the Stackup tab
Every recognised part has a value, or a variable you mean to tune
The parts table, and the report's unknown-value line
One number from the recognised schematic agrees with something you trust
