Components

Every component in the standard library — its symbol, what it does, and its parameters.

Symbols are rendered from the live drawing engine, with their connection leads and their pins shown unconnected — the component as you meet it in the palette, before anything is wired to it. Parameter tables are read from the component registry, so the defaults, units and on-schematic visibility below are the as-placed values by construction rather than by transcription.

Lumped elements

Resistor (R)

An ideal, frequency-independent resistor. R is the resistance.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Inductor (L)

An ideal inductor. L is the inductance. Couple two inductors with a Mutual element.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Capacitor (C)

An ideal, linear capacitor. C is the capacitance. For a voltage-dependent capacitance, see NonlinearC.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Series RLC (SRLC)

A resistance, an inductance and a capacitance in series, as one part. R, L and C are the three values; the branch impedance is R + jωL + 1/(jωC).

This is the shape a real capacitor takes above a few hundred megahertz, which is the usual reason to place one: a ceramic capacitor's datasheet gives an ESR and an ESL, and those go straight into R and L. The part is series-resonant at 1/(2π√(LC)), where its impedance falls to R — below that frequency it behaves as a capacitor, above it as an inductor. At DC the series capacitance makes the branch an open circuit.

Its pins sit exactly where a plain R, L or C's do, so you can swap one in for another without moving any wires. Its inductance can be coupled with a Mutual, which names the SRLC instance in place of an inductor.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Parallel RLC (PRLC)

The same three values in parallel — a tank. R, L and C all sit across the same two nodes, giving an admittance of 1/R + jωC + 1/(jωL).

At the parallel resonance 1/(2π√(LC)) the reactive parts cancel and the part is purely resistive at R, which is what makes it the natural way to enter a measured resonance: R sets the peak impedance, L and C set where it sits and how sharp it is. At DC the ideal inductor shorts it out.

Pin positions and Mutual coupling work exactly as they do for the SRLC above.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Series RL (SRL)

A resistance and an inductance in series, as one part: R + jωL. A real inductor, whose winding resistance is the R — and, unlike the SRLC you would otherwise place for the same job, with no third value on the schematic that nobody meant.

There is no series capacitance, so this branch does not open at DC: at ω = 0 it is simply R, which is what the physical part measures. Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Series RC (SRC)

A resistance and a capacitance in series: R + 1/(jωC). A real capacitor entered with its ESR, or a series RC damper across a resonance. At DC the capacitance makes the branch an open circuit.

It carries no inductor, so a Mutual naming one is refused rather than coupled — the refusal says so and names the part.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Series LC (SLC)

An inductance and a capacitance in series: jωL + 1/(jωC). The lossless series trap — its impedance falls to zero at 1/(2π√(LC)), which in a shunt arm is a notch. Below the resonance it behaves as a capacitor and above it as an inductor; at DC it is an open circuit.

Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Parallel RL (PRL)

A resistance and an inductance in parallel: an admittance of 1/R + 1/(jωL). The shunt form of a lossy coil, and the usual way a damped choke is entered. At DC the ideal inductor shorts it out.

Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Parallel RC (PRC)

A resistance and a capacitance in parallel: an admittance of 1/R + jωC. A leaky capacitor, or the shunt RC an equivalent circuit puts across a port. At DC the capacitor is an open and the part is R.

This is the one member of the RLC family that adds no branch current to the matrix — and therefore the one a Mutual cannot name.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Parallel LC (PLC)

An inductance and a capacitance in parallel: an admittance of jωC + 1/(jωL). The lossless tank — its impedance goes to infinity at 1/(2π√(LC)). For a tank with a finite peak impedance, use a PRLC and let R set the peak. At DC the ideal inductor shorts it out.

Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Ferrite Bead (Bead)

A two-terminal linear element: Rdc in series with a parallel L / Rp / Cp tank.

A bead is not an inductor and not a series RLC. The number a data sheet gives — "600 Ω at 100 MHz" — is an impedance, and the whole point of the part is that most of it is resistive at the frequency it is quoted at. That is what makes a bead absorb rather than reflect, and why it damps a supply rail where an inductor of the same reactance would ring against the decoupling capacitance. An inductor's loss is zero and a series RLC's is a constant R; a bead's rises from nothing at DC to a maximum at its ferromagnetic resonance and falls again above it.

Each element stands for a real mechanism:

Zero means not modelled for each of the three parallel elements, never "a short" or "a zero-ohm resistor". Rp = 0 removes the loss branch and leaves an ideal L; Cp = 0 removes the capacitive branch and the impedance goes on rising; L = 0 leaves a plain Rdc.

At DC the bead is Rdc and nothing else, because the inductive branch shorts the tank out. That is both the physics and what a DC operating point needs from this part — a bead in a supply rail must not open it.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Nonlinear Capacitor (NonlinearC)

A capacitor whose capacitance varies with voltage, C(V), modelled as a polynomial (Taylor) series. Enter the coefficients directly, or generate them from a C–V curve with the C–V Editor. C0 is the constant term; C1, C2, … are the higher-order coefficients, added in the editor or generated by the C–V Editor. Full treatment: The Nonlinear Capacitor & the C–V Editor.

The nets of an instance line, in this order. C(V) is evaluated at V(terminal 1) − V(terminal 2), so any odd coefficient (C1, C3, …) makes the two terminals distinct. With C0 alone the capacitor is linear and they are interchangeable.

Mutual Inductance (M)

Couples two existing inductors — named by instance — with a mutual inductance, the basis for transformers and coupled resonators. It has no pins of its own; Inductor1 and Inductor2 are the instance names of the two coupled inductors and M is the mutual inductance between them.

Either name may be any part that carries an inductor: an L, an SRLC, a PRLC, an SRL, an SLC, a PRL or a PLC — every one of them holds its inductor current on a branch the coupling can act on, and every one spells its value L. Naming anything else — an SRC or a PRC included, since neither has an inductor — is reported as an error when the design is elaborated.

No terminals — this component connects to nothing on the canvas.

Ideal Transformer (Transformer)

A lossless transformer with turns ratio N:1, primary to secondary:

V(p+) − V(p−) = N · (V(s+) − V(s−)), and the secondary current is N times the primary's, flowing the other way.

Four pins on the corners — the primary p+, p− on the left, the secondary s+, s− on the right — with the dots on p+ and s+: a voltage rising at one dotted end rises at the other. Seen from the primary, a load on the secondary looks N² times larger, so N=2 between 50 Ω ports matches a 200 Ω source to a 50 Ω load.

Being ideal, it has no winding inductance and no leakage: it passes DC as readily as RF, at every frequency, harmonic balance included. For a transformer whose windings have inductance — one that blocks DC and rolls off at low frequency — use two inductors and a Mutual.

The nets of an instance line, in this order.

Matching Network (Match)

A synthesised bandpass matching network placed as a single two-pin component, ground being the common return. Its whole design rides in a hidden Design parameter, so what it stamps is a property of the design rather than of the component type: the ladder it contains is the synthesised one minus whatever the two external terminations already supply, since absorbing those reactances is the point. Edit it in the Match Designer.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the R1 side and terminal 2 the R2 side. The synthesised ladder is stored R1-first, so swapping the two reverses every asymmetric match.

Sources

DC Voltage Source (Vdc)

A fixed DC voltage — gate and drain bias supplies. Vdc is the voltage.

The nets of an instance line, in this order. Vdc is the voltage at + relative to −.

Tone Source (VTone)

A single-tone (sinusoidal) voltage source for harmonic balance, with an optional DC offset. V is the tone amplitude, Freq the tone frequency, and Vdc a DC offset.

The nets of an instance line, in this order. V and Vdc are the voltage at + relative to −, and Phase is referred to the same pair.

Current Tone Source (ITone)

The current-source dual of VTone — a single-tone sinusoidal current source with an optional DC offset. I is the tone amplitude, Freq the tone frequency, and Idc a DC offset. Use it to drive a node with a known current rather than a known voltage: an ideal current source has infinite output impedance, so it sets the current through a branch and lets the network decide the voltage.

The arrow says which way the current goes. A positive I delivers current into pin 1 (the arrowhead end, the top pin as drawn) and draws it out of pin 2. Note this is the opposite of the SPICE I element, which sinks current from its first node; circuitRF uses one direction convention for every source it has, and the glyph states it so you never have to remember which.

Like VTone, the + button in the parameter editor turns it into a multi-tone source: the scalar I/Freq migrate to I[1]/Freq[1] and each further tone gets its own Freq[n], I[n] and Phase[n].

The nets of an instance line, in this order. A positive I is delivered INTO the + terminal and drawn out of the −, which is what the arrow on the + lead points at. Note this is the opposite sense to the VCCS's arrow, which is a controlled source and is drawn the way controlled sources are.

RF Power Source (P1Tone)

An RF source specified by available power with an internal source impedance — the natural drive for power-amplifier and loadpull work. It can also serve as an S-parameter port (via Num), and accepts per-harmonic source terminations Z[k] for harmonic source-pull.

• Num — S-parameter port index, sharing one pool with Term.
• Pavl — available power.
• Z — fundamental source impedance; Freq — fundamental frequency; Phase — phase.
• Z[k] — per-harmonic source termination: Z[0] is baseband/DC, Z[2] the second harmonic, and so on. Added in the parameter editor.

The nets of an instance line, in this order. + is the RF output and − the reference, normally ground — Term's own convention, since this is a source with Term's internal resistance in front of it. The source's internal impedance Z is in series with +.

Multi-Tone RF Power Source (PnTone)

The multi-tone sibling of P1Tone — an available-power RF source that injects several carriers at once from a single component, the natural drive for two-tone intermodulation work. A freshly placed PnTone is already a two-tone source (tones 1 and 2, at 1.99 and 2.01 GHz); the + and − buttons in the editor add and remove tones. Each tone has its own Freq[i], Pavl[i] and Phase[i]; all tones share one source impedance Z and the same per-band terminations Z[k], where each mixing product is terminated by the band its frequency falls in.

Unlike P1Tone, PnTone is not an S-parameter port — it has no Num. The tones a PnTone drives must match the tones declared on the Harmonic Balance analysis: the analysis owns the mixing grid, and the source just supplies power at those frequencies.

The nets of an instance line, in this order. + is the RF output and − the reference, normally ground — Term's own convention, since this is a source with Term's internal resistance in front of it. The source's internal impedance Z is in series with +.

Modulated RF Source (MOD_Source)

A modulated RF source — LTE, NR, CW, a pulsed-CW train, FSK (wireless M-Bus, Bluetooth LE), DBPSK (Sigfox), chirp spread spectrum (LoRa) or an imported I/Q waveform — for the Envelope analysis: ACLR/ACPR, EVM-style error, CCDF, AM-AM/AM-PM and two-carrier intermodulation with real signals rather than tones. One MOD_Source holds any number of carriers around its centre frequency Fc; Pavg is the total average available power behind the source impedance Z.

• Carrier[i] — one carrier, written as a description string, e.g. "NR;BW=20MHz;SCS=30kHz;Mod=64QAM;Off=-200MHz;P=0;Seed=1": the standard (LTE, NR, CW, FILE), channel bandwidth, NR subcarrier spacing, modulation, offset from Fc, relative power (dB) and the random-data seed. BW, SCS and Off take Hz, kHz, MHz or GHz; a bare number is in Hz. A FILE carrier plays a two-column I/Q text file, File= its path and Fs= its sample rate (taken from the file's # sample_rate_hz header when absent). A PCW carrier is a pulse train, "PCW;PRI=100us;PW=50us;Rise=0.5us;Fall=0.5us;Delay=10us;Off=0;P=0": the pulse repetition interval, the width (50 % to 50 %), the 10–90 % edge times and the off-time before the rising edge (centred in the PRI when absent). Its time fields take s, ms, us (or µs) or ns; a bare number is in seconds. A PCW carrier must be the source's only carrier, and Pavg is then the pulse-top power, not the record average: see Pulsed CW. An FSK carrier is binary continuous-phase FSK, "FSK;Rb=100kbps;Dev=45kHz;BT=0.5;Data=PN9;Off=0;P=0": the bit rate (bps, kbps or Mbps), the peak deviation, the Gaussian filter's BT (absent: no filter) and the data — PN9, PN15 or a fixed pattern such as 10110100, one period of which is the record. It too must be the source's only carrier: see FSK. A DBPSK carrier, "DBPSK;Rb=100bps;Data=PN9;Off=0;P=0", takes the same Rb and Data (the Sigfox uplink: DBPSK), and a CSS carrier, "CSS;SF=7;BW=125kHz;Off=0;P=0", a spreading factor and a chirp bandwidth (LoRa: CSS); each must be the source's only carrier.
• Record — periodic record length (s), whole 0.5 ms slots. Clip — target PAPR (dB) for clip-and-filter; absent means unclipped (the natural OFDM PAPR, about 11–12 dB). Shaping — out-of-channel spectral floor (dBc), or off.

Select the source and press Design signal… in the inspector to open the Signal Designer: the carriers and presets, or a custom I/Q file of your own, with the spectrum, the CCDF and the EVM of the signal before you simulate it.

In a harmonic-balance or loadpull run a MOD_Source is a CW tone at Fc carrying Pavg — the signal's average power, or for a pulsed-CW source the pulse-top power, the steady state of a pulse that never ends; in an S-parameter run it is the passive impedance Z.

The nets of an instance line, in this order. + is the RF output and − the reference, normally ground — Term's own convention, since this is a source with Term's internal resistance in front of it. The source's internal impedance Z is in series with +.

Voltage-Controlled Current Source (VCCS)

An ideal transconductance: the current it delivers is G times the voltage across a separate, purely-sensing control pair, optionally delayed by T.

I = G · e^(−jωT) · (V(ctrl+) − V(ctrl−))

Four terminals in two pairs — the output pair (out+ top, out− bottom) carries the current, and the control pair (ctrl+, ctrl−, on the left) senses the controlling voltage. The control pair draws no current at all, which is what makes the source ideal and what makes the device unilateral: nothing travels backwards through it. G is the transconductance, in siemens.

T is a time delay (hidden until you set it; 0 is no delay). It multiplies the gain by e^(−jωT): unit magnitude, and a phase lag that grows in proportion to frequency, so the source has a constant group delay of T. A positive T lags. DC is unaffected, since e^0 = 1. T is the only source of phase: G itself is a real number.

The arrow says which way the current goes, and it points down: a positive G and a positive control voltage draw current in at out+ and out at out−. That is the SPICE G element's own direction, and the way a small-signal transconductance is drawn in a device model — the controlled source sinks drain current from the drain node. So a VCCS across a grounded load resistor is inverting, and a 50 Ω, G = 10 mS stage measures S21 = −0.25.

Note the VCCS's arrow points the opposite way to ITone's. That is not an inconsistency to squint past: ITone is an independent source and delivers current to its arrow pin, while the VCCS is a controlled source drawn the way controlled sources are drawn. Read each symbol's own arrow.

The nets of an instance line, in this order.

Voltage-Controlled Voltage Source (VCVS)

An ideal voltage gain: the voltage it holds across its output pair is E times the voltage across a separate, purely-sensing control pair, optionally delayed by T.

V(out+) − V(out−) = E · e^(−jωT) · (V(ctrl+) − V(ctrl−))

Four terminals in two pairs, laid out exactly as the VCCS's are — the output pair (out+ top, out− bottom) and the control pair (ctrl+, ctrl−, on the left), which draws no current at all. E is a voltage ratio and carries no unit.

T is a time delay, exactly as on the VCCS: the gain becomes E · e^(−jωT), and E itself is a real number.

The two tiles differ in one thing: what the diamond carries. The VCCS's arrow points at the current it delivers; the VCVS has a ± pair down its axis instead, because there is no current direction to point at. A VCVS states a potential difference and whatever current the rest of the circuit draws through it flows — including none, if nothing is connected across the output pair. That is the ideal source's own behaviour, not a limitation.

Being ideal, its output impedance is zero: it holds E times the control voltage no matter what it is loaded with. Put a series resistor after it if you want a source with an impedance.

The nets of an instance line, in this order.

Operational Amplifier (OpAmp)

A triangle with the inverting input in− above the non-inverting input in+, and the output out at its point, referenced to ground.

With A=0, the default, it is ideal — infinite open-loop gain. Its inputs draw no current and are held at the same voltage, and the output delivers whatever current that takes, so the feedback network alone sets the gain: an inverting stage with Rin and Rf has a gain of exactly −Rf/Rin.

A non-zero A makes it a finite-gain amplifier, V(out) = A · (V(in+) − V(in−)), with an output resistance Rout behind it. As A grows, the answers converge on the ideal ones. Rout acts only with a finite A.

It is linear and the same at every frequency: there is no bandwidth, slew rate or output swing limit, so an op-amp left without negative feedback has an output nothing bounds. For a gain that rolls off, put the roll-off in the circuit around it.

The nets of an instance line, in this order.

Operational Amplifier with supply pins (OpAmp5)

The same op-amp with its supply pins drawn, V+ above and V− below, for schematics that wire the supplies. They carry no current and change nothing: the op-amp behaves exactly as the three-pin tile does. A supply pin left connected to nothing is a node nothing sets, so connect both, or place the three-pin OpAmp instead.

The supply pins are cosmetic only.

The nets of an instance line, in this order.

Terminals & ports

Ground (GND)

The global reference node (net 0). No parameters.

Term

An S-parameter port: a numbered, reference-impedance termination where the simulator excites and measures. Num is the port index, auto-assigned at placement; Z is the reference impedance. See Pins, Ports & Terms for how it differs from a Pin.

Outside S-parameters a Term is a load of Z to its reference: its resistance (the real part of Z) in a DC run, and Z at every harmonic in a harmonic-balance or loadpull run. A bias or a current returning through it flows, as it would through the instrument it stands for. Put a DC block in front of a Term on a biased node, exactly as on a bench. A Term inside a cell is ignored in every analysis.

The nets of an instance line, in this order.

Grounded Term (TermG)

A Term whose second port is permanently grounded, presenting as a one-port. It is a packaging convenience rather than a parallel model: it uses Term's own engine component and glyph exactly, with the ground symbol drawn at Term's port-2 location, so a schematic that swaps Term + GND for a TermG is electrically identical.

One terminal, + — an instance line writes a single net.

Pin

A cell's interface terminal — connectivity only, no electrical model. Pins on a cell's symbol are how the cell connects to the parent that instances it. Num is the interface port index, auto-assigned; Name is an optional label, and extraction uses P{Num} when it is blank. An optional Polarity of Plus or Minus, set in the editor, forms a differential pair sharing one Num.

One terminal, 1 — an instance line writes a single net.

Current Probe (IProbe)

A 0 V series ammeter placed in a branch to read its current. Its instance name — Iout, say — is how measurements reference that current: I("Iout", 1). No parameters.

The nets of an instance line, in this order. A 0 V ammeter: the current it reports flows np to nm. Swapping the two negates every measurement that reads it.

No parameters.

Voltage Probe (VProbe)

A one-terminal voltage probe. Drop it anywhere on a wire and that net is reported under the probe's instance name — Vout, say. That name is what the trace picker lists and what a measurement expression reads: V("Vout").

It is a label, not a part. It has one terminal, so it cannot bridge two nets; the elaborator builds no model for it, so it stamps nothing; and a design simulates identically with every VProbe deleted. Placing one can never change an answer — it can only add a name to it.

On an unnamed wire the probe's name becomes the net's name. There is one row in the results, called Vout, and no n7 beside it — the automatic name was never a name anyone chose, and two rows for one point in the circuit is one row too many.

On a wire you have already labelled, both names appear. The label is not overwritten: a wire labelled n_drain with a Vout probe on it shows up twice — as n_drain and as Vout — carrying the same voltage. The probe is an alias there, and either name plots and measures the same node.

Two rules keep the names unambiguous, and breaking either refuses the run rather than reporting:

• Two VProbes may not share a name.
• A VProbe may not share a name with a net.

A VProbe that touches nothing is reported in the Messages panel and drops out of the results, rather than reporting a plausible number for a point you never probed. So is one placed on ground, which is 0 V by definition.

It is the one component you can drag off a wire. Every other symbol takes its wires with it when you move it, because moving the picture must never re-wire the circuit. A probe has nothing to re-wire, so dragging it leaves the drawing exactly as it was and puts the probe wherever you dropped it — pick it up, look somewhere else, run again, with no repair work in between. Rotating it behaves the same way, and a wire dragged out from under a probe simply leaves it behind.

Select the probe and its wire together and they move as one, so the probe stays on the net.

One terminal, v — an instance line writes a single net. One terminal, at the arrow's tip. It taps the net it touches and names it after the instance; there is no second terminal to get the wrong way round, and nothing it can short together.

No parameters.

Stability Probe (WSProbe)

A stability probe, placed in a node so that it splits the node into a generator-side terminal (G) and a load-side terminal (L). It implements T. A. Winslow, General Circuit Analysis Using The WSProbe (2023); every quantity below is that document's, under its own name.

Electrically it is an IProbe — a 0 V short — and it is placed the same way: drop it onto the wire whose node you want to look at, and circuitRF deletes the stretch of wire between its two pins so the probe breaks into the run instead of being shorted by it. It perturbs nothing, so a design simulates identically with every WSProbe deleted. It takes no parameters.

The letters are the orientation. G is the generator-side terminal and L the load-side one: ZG looks out of G, ZL out of L. Rotating or mirroring the symbol moves the drawing and never the pin order, so swapping the two means swapping the wires — which swaps every G/L-labelled output and negates nothing else.

What it produces is not a number but a matrix. An S-parameter run with any WSProbe in it writes a wsp cube — 2N x 2N for N probes — and six named outputs per probe: H0 and Y0, the driving-point impedance and admittance; ZG and ZL, the bidirectional impedances; LG, the bilateral loop gain; and F = 1 - LG. Two stability margins, SM_Y0 and SM_H0, come with them. Everything else the document derives — every other loop gain, the reduced two-port at the probe, the probe-pair blocks, the global loop gains over a set of probes — is post-processing of that one matrix, and is available in the Data Display's trace card and in a measure line.

Reading a node for stability is two plots, not one. Plot 1/H0 and 1/Y0 on a polar chart and look for a clockwise crossing of the negative real axis; the trace card reports the frequencies it finds, or none. Both must be checked, because a zero can hide the pole in one of them but never in both — a series resonance shows in 1/Y0 alone and a parallel one in 1/H0 alone.

The stability margin is a distance, and the search is the detector. SM_Y0 and SM_H0 are unitless numbers in [0, 1], shown in dB (20*log10), and the trace card prints each one's minimum beside the crossing search that pairs with it. A node with positive resistance on both sides can never read below -12 dB, so anything under that line certifies negative resistance on one side; the run reports any probe whose margin falls below the analysis' MarginThreshold (default -15 dB) as worth looking at. That report is a note, not a warning: a low margin is somewhere to look, not a failure.

The WSProbe has its own chapter — every quantity with its equation, the probe pairs, the global loop gains, the stability envelope, the probe under harmonic balance, the NDF, and an appendix on stability analysis itself.

The nets of an instance line, in this order. G is the generator-side terminal, L the load-side. ZG looks out of G, ZL out of L; swapping them swaps every G/L-labelled output and negates nothing else.

No parameters.

Oscillator Probe (OscProbe)

The marker an oscillator analysis needs: it says where in the circuit the oscillation is looked for. Place exactly one, where the oscillation is strong:

• Mode=series (the default): in the oscillator's loop, the way an IProbe is placed. Drop it onto a wire and it breaks into the wire.
• Mode=shunt: across the resonator, often from the tank's live side to ground.

In every other analysis it does nothing: a short in series, an open in shunt. So a design runs the same with it as without it.

Under the oscillator analysis it holds a generator at the oscillation frequency only. In shunt it is a voltage generator, and the analysis finds the amplitude and frequency at which it draws no current. In series it is a current generator, and the analysis finds where it holds no voltage. Either way the generator does no work at the answer, so the circuit is oscillating on its own. Its two terminals are interchangeable.

The nets of an instance line, in this order. Interchangeable. In series (Mode=series) it sits IN the oscillator's loop; across the resonator (Mode=shunt) it joins the two sides of the tank, often one of them ground.

Tuner / SourceTuner / LoadTuner

A programmable RF termination. The three variants are the same engine component with different glyphs and net ordering — match the symbol to its role. SourceTuner sits on the source side, LoadTuner on the load side.

• Z[1] — the fundamental termination. Required, and it accepts complex literals such as 50+j*10. Add Z[2], … in the editor, or G[k] to give a reflection coefficient instead.
• Zdefault — the catch-all termination for harmonics not otherwise specified, and the impedance the tuner presents at DC.
• Z0 — the reference impedance for any G[k] entry.
• BiasTee — on or off, chosen from a picker. on builds the internal bias-tee and DC supply, which the loadpull directive requires. With it off the tuner is RF-only: there is no DC path through it to the reference node.
• Vbias — the DC bias at the DUT-facing port when the bias-tee is on.
• ShowBias — true or false, chosen from a picker. Display only: it draws the bias-tee on the glyph and never reaches the engine, so the extracted netlist is identical either way.

One terminal, 1 — an instance line writes a single net.

Which analyses a tuner works in

All five that terminate a circuit: DC, S-parameters, harmonic balance, loadpull and loadpull pursuit. It is an ordinary linear component, so a parametric sweep wrapping any of them sweeps it like anything else.

How its frequency response is defined

A tuner is not a fitted network. It presents the impedance you declared, exactly, with no interpolation between entries and no roll-off. Which entry it presents depends on the analysis:

So the answer to "what does Z[2] do in an S-parameter run?" is nothing: declare the band you care about in Z[1], and use several S-parameter analyses if you want several terminations.

In loadpull and pursuit, the SourceTuner is also the RF generator

A loadpull run needs a drive as well as terminations, and the SourceTuner supplies it: the loadpull and pursuit engines assign it the source role, which stamps a single-tone RF generator inside it, behind the impedance it presents. The generator is calibrated to available power — |V_s| = √(8·P_avl·Re Z₁) — so the power you ask for and the impedance the DUT is driven from stay consistent as either one moves across the sweep.

The drive level is not a tuner parameter. There is no Pavl row on the component, because the sweep over drive belongs to the run, not to the part. The ladder is set in the analysis: Pin start (dBm), Pin max (dBm) and Pin step (dB) in the Loadpull and Loadpull Pursuit setup, walked upward from the start until compression is reached or the cap stops it.

Transmission lines

Ideal Transmission Line (TLIN)

An ideal transmission line of characteristic impedance Z, stated one of two ways:

• Electrical (the default): electrical length E at a reference frequency F. Optional loss A is the total in dB at F, scaling in proportion to frequency.
• Physical: length L with effective permittivity Eeff (default 1, an air line), so the electrical length is θ(f) = 2π·f·L·√Eeff / c₀ with no reference frequency needed. Loss is per unit length: Ac (conductor, scaling as √f) and Ad (dielectric, scaling as f), both in dB/m at F and both 0 by default.

A line states E or L, never both; Eeff below 1, A together with L, and Ac or Ad without F are refused. In the parameters dialog, Use physical length / Use electrical length switches form, converting at F (or at 1 GHz when there is none) so the line does not change; the new L is written in the technology's length unit. For a physical-form line, circuitrf explain reports the electrical length it resolves to at F.

TLIN:TL1 a b Z=50 Ohm L=25 mm Eeff=3.2 Ac=4 Ad=2 F=2 GHz

The nets of an instance line, in this order. The two terminals are interchangeable: the line is uniform, so neither end is the input.

Coupled Line (CLIN)

An ideal, lossless pair of coupled transmission lines over a common ground, specified by its even-mode impedance Ze, odd-mode impedance Zo and electrical length E at a reference frequency F. Like TLIN it has no substrate and no layout; it is the four-port to reach for when designing a coupler or a coupled-line filter section before committing to a geometry.

• Match. All four ports are matched to Z0 when Ze · Zo = Z0²; the default 69.37 Ω / 36.04 Ω pair is matched to 50 Ω.
• Coupling. At a quarter wave (E = 90° at F) the coupled-port voltage is (Ze − Zo) / (Ze + Zo) — about −10 dB for the defaults.
• Inhomogeneous media. Eo is the odd mode's electrical length. Left blank, both modes share E, which is the homogeneous (stripline) case with ideal isolation. Set it shorter than E to model a medium such as microstrip, where the odd mode travels faster and the directivity is finite.

The nets of an instance line, in this order. Terminals 1 and 2 are the two ends of one line, 3 and 4 the two ends of the other; 3 sits beside 1 and 4 beside 2. Driving 1 of a matched pair, 2 is the through port, 3 the coupled port and 4 the isolated port.

Broadside-Coupled Stripline (BCLIN)

A pair of strips on two adjacent conductor layers, one above the other, between two ground planes in one dielectric — the offset broadside-coupled stripline used for tight (3 dB and closer) couplers. Its pins are CLIN's: 1 and 2 are strip A (the upper one), 3 and 4 strip B, with 3 beside 1.

• Geometry. W is the strip width (both strips), O the lateral offset between their centres (0 puts one directly over the other) and L the length. The cross-section — Hs between the strips' facing surfaces, Ha from strip A up to its ground, Hb from strip B down to its ground, the thickness T and Er — starts empty, which means from the stackup: LayerA (default: the first signal conductor with another signal conductor directly beneath it and a ground plane above and below) and LayerB (the next conductor down) are resolved on the technology, every layer between two surfaces counting toward their spacing. Typing a value into one of those rows overrides the stackup for that row only; with no technology the run says which rows take their standalone defaults.
• Physics. The cross-section is solved by circuitRF's own 2D quasi-static field solver (finite differences on a graded grid, thick strips, the two grounds), once per geometry. Both modes travel at c/√εr; the even- and odd-mode impedances follow from the capacitance matrix. An asymmetric stack (Ha ≠ Hb, unequal thicknesses) is described by the symmetric average of the two strips, and the run says so when they differ by more than 5 %.
• Loss. Conductor loss is integrated over the solved surface-charge distribution (both strips and both grounds), dielectric loss is exact for the homogeneous medium.

The nets of an instance line, in this order. Terminals 1 and 2 are the two ends of one line, 3 and 4 the two ends of the other; 3 sits beside 1 and 4 beside 2. Driving 1 of a matched pair, 2 is the through port, 3 the coupled port and 4 the isolated port.

Microstrip Line (MLIN)

A physical microstrip line on the current technology's substrate: W is the conductor width and L the length. Unlike TLIN, its impedance and loss follow from the geometry and the substrate rather than being stated. The parameters dialog shows the Z0 (and εeff) the current W gives on the resolved substrate; type a Z0 there instead and W is set to the width that gives it, as one undoable edit.

The length can be stated electrically instead, as E at F in place of L, exactly as a TLIN's is: Use electrical length in the parameters dialog converts the current L at the line's own εeff, and Use physical length converts it back, so switching never changes the line a run simulates. CPWG and SLIN have the same button. Layout always draws the physical length.

The nets of an instance line, in this order. The two terminals are interchangeable: the line is uniform, so neither end is the input.

Grounded Coplanar Waveguide (CPWG)

A coplanar waveguide over a ground plane: a strip of width W with ground copper on the same layer a gap G from each edge, and a plane under the substrate. The substrate and the backing plane come from the technology, as an MLIN's do; the gap is the line's own. When the coplanar ground is far from the strip the line is a microstrip, and CPWG gives the same answer an MLIN would. The parameters dialog shows the Z0 and εeff at the top frequency of the schematic's S-parameter sweep, and a Z0 typed there sets W. Against a 2-D field solve its Z0 is within about 2 % over the gaps and widths PCB and MMIC lines use. Update Layout from Schematic draws the strip, and a ground strip as wide as the strip on each side of it; the vias that tie those grounds to the plane are yours to add.

The nets of an instance line, in this order. The two terminals are interchangeable: the line is uniform, so neither end is the input.

Stripline (SLIN)

A strip of width W buried between two ground planes, centred or offset. The planes are the nearest ground-designated conductors above and below SignalLayer, and the dielectric between them sets the two heights, εr and the loss — when that dielectric is several layers of different εr, the line uses their thickness-weighted mean and says so. A layer without a plane on each side cannot carry a stripline, and the line is refused rather than simulated as something else. The parameters dialog shows its Z0; a Z0 typed there sets W. Update Layout from Schematic draws the strip on SignalLayer.

The nets of an instance line, in this order. The two terminals are interchangeable: the line is uniform, so neither end is the input.

Swapping one line type for another

Right-click a TLIN, MLIN, CPWG or SLIN and choose Swap Line Type to turn it into one of the others in place, or choose the type from the type field at the top of its parameters dialog. With several lines selected, the context menu swaps all of them as one undo step; a line that cannot be swapped is named in Messages and the rest still swap.

The instance name, its wiring and its position stay the same, and so do W and L — the impedance follows from the new line type, and the parameters dialog shows it.

• To CPWG, the gap is the one measured off the artwork when the line came from Create Schematic from Artwork; otherwise the line's earlier G, if it had one; otherwise you are asked for it.
• To TLIN, Z and Eeff are what the old line has at the top frequency of the schematic's S-parameter sweep, with its loss as Ac and Ad; the TLIN is in its physical form.
• From TLIN, W is the line's earlier width when it had one, and otherwise the width that gives Z at that frequency (Messages says when it was worked out this way). An electrical-form TLIN's E becomes a length.
• To SLIN, the signal layer needs a plane above and below it; on any other layer the swap is refused and the line is left as it was.

Nothing is lost: a parameter the new type does not have (CPWG's G, a TLIN's Z, a layer choice) is kept with the component, so swapping straight back gives the original line exactly. Each type takes its substrate from the technology. An MBEND, MTEE, MCROSS or MTAPER next to a swapped line stays a microstrip discontinuity, and Messages says so.

Coupled Microstrip Lines (MCLIN)

A symmetric pair of edge-coupled microstrip lines on the technology's substrate: strip width W, edge-to-edge gap S and length L. Its pins are CLIN's (1/2 line A, 3/4 line B, 3 beside 1), so a CLIN in a schematic can be replaced by one without rewiring.

The even- and odd-mode impedances and effective permittivities come from the Kirschning–Jansen coupled-microstrip equations, with their frequency dispersion and a correction for the strips' thickness; the two modes keep their own εeff, so the odd mode is faster and the isolation of a coupler is finite, as on a real board. Conductor, roughness and dielectric loss are MLIN's, per mode. The published range is W/h and S/h from 0.1 to 10 and εr up to 18; outside it the result is still computed and the run says it is an extrapolation. On placement W starts at the workspace's 50 Ω width and S at the same value.

The nets of an instance line, in this order. Terminals 1 and 2 are the two ends of one line, 3 and 4 the two ends of the other; 3 sits beside 1 and 4 beside 2. Driving 1 of a matched pair, 2 is the through port, 3 the coupled port and 4 the isolated port.

Broadside-Coupled Microstrip (MBCLIN)

BCLIN's broadside pair without the upper ground: strip B is buried in the dielectric Hb above the ground plane, strip A sits Hs above it — on the top surface by default (Hd empty), or buried too when Hd or the stackup puts dielectric over it — and there is air above. Its pins are CLIN's.

Because the medium is not uniform, the field solver runs twice — with the dielectric and with air — and each mode gets its own impedance and its own εeff; as with MCLIN the modes travel at different speeds, which limits the directivity. The two strips are never symmetric here (they sit at different heights), so the pair is always described by the symmetric average of the two, and the run says how far apart they are. The cross-section rows and LayerA/LayerB follow the stackup exactly as BCLIN's do, with the one ground plane below strip B.

The nets of an instance line, in this order. Terminals 1 and 2 are the two ends of one line, 3 and 4 the two ends of the other; 3 sits beside 1 and 4 beside 2. Driving 1 of a matched pair, 2 is the through port, 3 the coupled port and 4 the isolated port.

Microstrip Bend (MBEND)

A right-angle microstrip bend of width W, optionally mitred, modelled with its discontinuity rather than as an ideal corner.

The nets of an instance line, in this order. The two terminals are interchangeable. One width and one angle describe the whole bend, so the pins differ only in which way it turns on the canvas.

Microstrip Curve (MCURVE)

A radiused (curved) microstrip bend: width W, turn Angle (counter-clockwise positive, as MBEND's) and Radius, the centre-line radius. Where MBEND is a corner with a discontinuity, a curve has no corner — it is modelled as the line it nearly is, an MLIN of the same width over the effective length (R − 0.2·W)·|Angle|. The electrical path is a little shorter than the drawn centre line because the current favours the inner edge.

That rule is published for Radius between 3W and 7W. Outside it the result is still computed and the run says it is an extrapolation; below 2W a bend is more than a change of length and the run tells you to EM-simulate it. A radius below W/2 cannot be drawn and is refused. The reference planes are the two ends of the arc, so an MCURVE butts straight onto an MLIN with no overlap to subtract. In layout it is drawn with true arc edges, which EM, DRC and the exporters flatten to the technology's own tolerance.

The nets of an instance line, in this order. The two terminals are interchangeable. One width, one radius and one angle describe the whole curve, so the pins differ only in which way it turns on the canvas.

Microstrip Mitred Bend (MMITER)

A chamfered (mitred) microstrip corner: width W, turn Angle (counter-clockwise positive, as MBEND's, anywhere up to 120°) and miter M. M is the fraction of the corner's outer-to-inner diagonal that is cut away, measured from the outer corner — the Douville–James definition — so at 90° M = 0.5 runs the cut corner to corner across the W×W corner square, and larger values cut deeper. On placement M starts at the Douville–James optimum for the workspace's 50 Ω line, which is the cut that best cancels the corner's reflection on a right-angle bend; at other angles that same fraction is a reasonable starting point rather than an optimum.

Electrically the bend is the line it is drawn as — an MLIN of the corner's own centre-line length — plus a small correction for what the corner does that a straight line would not. That correction comes from a table characterised with circuitRF's own planar EM over W/h, εr, angle and miter, and is interpolated in between, so any angle and miter inside the range work, not only 45° and 90°.

The pins sit where the strip is full width again: at 90° with M up to 0.5 these are the edges of the W×W corner square (MBEND's planes); a deeper chamfer moves them out a little, and the extra line is part of the part. Draw the MLINs either side from the pins. W/h between 0.35 and 7 and εr between 2.2 and 13 are characterised; outside that the result is still computed and the run says it is an extrapolation. An angle past 120° or a miter deeper than the table covers (0.6 at 45° and below, 0.8 from 90°) is refused. Conductor thickness enters through the line part only.

The nets of an instance line, in this order. The two terminals are interchangeable. The chamfer is symmetric about the corner's bisector, so the pins differ only in which way it turns on the canvas.

Microstrip Gap (MGAP)

The end-to-end gap between two microstrip lines of the same width: W is the width of the line on each side and S the gap, edge to edge, from one line's end to the other's. Use it wherever a gap is part of the design — the coupling between the resonators of a gap-coupled filter, an end-coupled feed, or a DC break in a line — so that the gap is a value you can see, sweep and optimise rather than a distance two lines happen to be apart. The two terminals are interchangeable.

Electrically the gap is a series capacitance across it and a shunt capacitance from each line end to ground, from closed-form fits that are stated over 0.5 ≤ W/h ≤ 2, 0.1 ≤ S/W ≤ 1 and 2.5 ≤ εr ≤ 15. Outside that range the result is still computed and the run says it is an extrapolation. The capacitances do not change with frequency and carry no loss. Checked against circuitRF's own electrostatic EM solve on a 0.508 mm, εr 3.66 substrate: up to W/h = 1 the gap's |S21| is within 0.5 dB and its phase within 0.5°; at W/h = 2 the closed form reads the series capacitance 8–14 % low (|S21| up to 1.3 dB low), and at W/h = 2 with S = W — both ratios at the edge of the range — it reads it 43 % low, 4.9 dB in |S21|. Where the gap is the design, check it by EM there. S must be greater than zero: a gap of zero is two lines touching, and the simulation refuses it.

In the layout, MGAP draws no copper. Its layout is its two pins, S apart and each W wide, and the lines placed on either side are the metal — so when the layout is updated from the schematic, the two line ends land exactly S apart. Its two pins are on different nets, so LVS reads the gap as a designed break, not an open.

The nets of an instance line, in this order. The two terminals are interchangeable: the gap is symmetric about its centre, so neither side is the input.

Microstrip T-Junction (MTEE)

A three-port microstrip T-junction. W1, W2 and W3 are the widths of the three arms, and L1, L2 and L3 their lengths from the junction's centre to each pin — the shape the layout draws.

The arms are simulated as microstrip lines, with the junction model between them. A through arm carries L1 − W3/2 (or L2 − W3/2) of line, the branch L3 − max(W1, W2)/2: the junction model starts where the crossing arm's edge is. When the branch reaches no further than the through line's edge, the tee is a straight line with pin 3 on it, and it simulates as exactly that — two lines of L1 and L2 meeting at pin 3 — so with pin 3 open it gives the same answer as an MLIN of L1 + L2. Any longer branch brings the junction model in.

A tee with no L values (from a file saved before they existed) simulates the junction alone, and the run says its arms are not simulated.

The nets of an instance line, in this order.

Microstrip Cross-Junction (MCROSS)

A four-port microstrip cross-junction, with a width (W1–W4) and a length from the centre (L1–L4) per arm.

The arms are simulated as microstrip lines with the junction model between them, as for the MTEE: arms 1 and 3 carry L − max(W2, W4)/2 of line, arms 2 and 4 L − max(W1, W3)/2. When arms 2 and 4 both stop at the edge of arms 1 and 3, the cross is a straight line — the lines of L1 and L3 with pins 2 and 4 on it — and with those pins open it equals an MLIN of L1 + L3. The same holds the other way round. A cross with no L values simulates the junction alone, and says so.

The nets of an instance line, in this order.

Linear Microstrip Taper (MTAPER)

A linearly tapered microstrip line running from width W1 to width W2 over length L.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the W1 end and terminal 2 the W2 end.

Klopfenstein Taper (MKLOPF)

A Klopfenstein-taper microstrip line — the taper profile that gives the shortest line for a stated in-band ripple. Specify the two impedances (or the two widths), the maximum reflection GammaMax, and either a length or a 3 dB corner frequency.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the Z1 end and terminal 2 the Z2 end.

Via (VIA)

A plated via changing layers: terminal A lands on FromLayer, B on ToLayer. Its inductance, resistance and capacitance are computed from the technology's stackup — the barrel length, the drill it belongs to, the ground planes it passes and any stub where the drill runs on — so none of them is typed. Every row may be left empty to follow the technology; the parameter dialog shows the L, R and C that result. The formulas, where they hold and how they compare with a 3D solve are in Vias.

The nets of an instance line, in this order. Terminal A lands on FromLayer and terminal B on ToLayer. Swapping them swaps which layer each end is on, and which end a stub hangs from when the drill runs past a layer.

Via to Ground (VIAGND)

A via from a pad down to a ground plane — the return of a shunt part, with the pad's capacitance across it. One pin, on FromLayer; the far end is GroundLayer. See Vias for what it replaces.

One terminal, A — an instance line writes a single net. One terminal, A, on FromLayer. The far end is ground: the via lands on GroundLayer.

Test Point Pad (TESTPAD)

A round test-point pad on an RF line: a pad of diameter D on PadLayer — by default the lowest signal conductor, the board's far side — fed either through a via at its centre from ViaFrom (Feed = Via) or by a short stub leaving it on one side (N, E, S or W, FeedW wide). Terminal 1 is the feed — the via on ViaFrom, or the stub's end — and terminal 2 is the pad centre. Leave terminal 2 open for a test point that is not in use, or continue it to a connector.

The pad loads the line with its capacitance to the nearest plane and the via's inductance, and the two resonate. The model is an estimate: the pad's capacitance to the nearest plane on each side, as a disc over a plane, with the dielectrics between combined in series; the via's inductance over its length, with the barrel's capacitance to each plane it passes. Every inner conductor counts as a plane under the pad unless ClearLayers names it. Messages gives the values and the resonance once per run. Rows that do not apply to the chosen Feed are greyed out in the parameter dialog: FeedW through a via, and ViaFrom, Drill, InnerPadD and AntipadD for a side-fed pad.

Unused pads on the via. Board CAD usually keeps a pad on every conductor a via passes, joined to nothing, and each adds capacitance across its antipad. Set InnerPadD to their diameter and the model counts them (and the layout draws them) on every conductor between ViaFrom and PadLayer that ClearLayers does not name; AntipadD is the clearance round the via in each plane (empty: the technology's). Messages gives their share separately. Removing unused pads at manufacture removes it.

Cut-outs. ClearLayers names the conductors whose plane gets a round cut-out ClearD across under the pad; the parameter dialog lists the technology's conductors to tick. Where the nearest plane is cut, the pad faces it over the ring outside the hole and the next plane through the hole, so its capacitance falls as ClearD grows and settles once the hole is a little wider than the pad. ClearD = 0, or one no wider than the via's AntipadD, cuts nothing: those planes are modelled as ordinary planes, and Messages says so. In a plane the via passes, its barrel sees the larger of ClearD and AntipadD. Cut-outs are not drawn as shapes: a ground pour drawn by Update Layout or Draw Ground Pour cuts them, as it cuts a via's antipad. On a board whose planes are drawn artwork, right-click the placed pad and choose Cut Clearances into Planes.

An EM port at the centre. With Centre = Port the layout carries an EM port at the pad's centre, an internal port to ground numbered PortNum (empty: the next free number). An EM setup of the board picks it up from inside the placed part — in 3D as a sheet from the pad to the nearest plane with metal there, through any cut-out — so the pad can be solved with and without each cut-out before a board is built. See Ports a component carries.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the feed — the via on ViaFrom, or the end of the side stub — and terminal 2 is the pad centre. Leave 2 open for a test point that is not in use, or continue it to a connector.

GSG Probe Pad (GSGPAD)

A ground-signal-ground probe pad and the microstrip line leaving it, for an RF probe landing on a die or a board. The signal pad sits between two ground pads at Pitch — centre to centre, the probe's own pitch — each ground pad holding NVia vias to the plane in a row along it, and a line W wide and L long leaves the signal pad. Terminal 1 is where the probe's signal tip lands, the middle of the signal pad; terminal 2 is the line's far end. Put the measurement port on terminal 1. In the layout the probe approaches from the side away from the line.

The model is MLIN: half the signal pad, PadW wide and PadL/2 long, then the line, cascaded. The ground pads are ideal ground at the probe's tip, which is where a calibrated probe puts its reference; their vias are drawn but are not part of the circuit. It is a microstrip, never a coplanar line: the ground pads stop at the signal pad and do not run along the line. The vias are a Via to Ground's, landing on the plane under the line — on a die, backside vias — with the technology's drill and pad; a ground pad grows longer when its row of vias needs the room. NVia = 0 draws no vias, for ground pads grounded some other way.

W is set to the 50 Ω width when the part is placed on a technology. Pitch, PadW and PadL are in µm and are the probe's, so no technology changes them.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is where the probe's signal tip lands, the middle of the signal pad, and terminal 2 the far end of the line. Put the measurement port on terminal 1.

Wirebond (wBond)

A wirebond design placed as a single component. Its symbol is generated from the design it carries — two pins per wire array plus a REF pin — so both the pin count and the pin names are properties of that design rather than of the component type. The wires themselves are drawn in the layout view, not here.

Terminals are set by Arrays; this component has no fixed pin geometry of its own.

MMIC passives

The parts a die is drawn from. Like a microstrip line, each one takes its process from the workspace technology — you state only the geometry, and the stackup supplies the film's permittivity and thickness, the metals, the sheet resistance, the air-bridge height and the substrate. Each has a built-in layout cell of the same name, so a schematic of them generates a layout the way a board's microstrip does, with every terminal on the metal that lies on the substrate.

On a technology that lacks what a part needs — a board has no MIM film, for instance — the run says which piece is missing and uses the shipped GaAs process's numbers instead.

The properties panels show what the geometry comes out to, as a value you read rather than type: a TFR's resistance, a MIMCAP's capacitance and a spiral's inductance, each computed by the same model a run uses, on the technology's process. It follows every edit as you type. In a layout's Inspector and Component Properties it is the greyed row after the geometry. A schematic's Parameters panel also shows a spiral's series resistance, at DC and at 10 GHz, where the skin effect has raised it.

MIM Capacitor (MIMCAP)

A metal-insulator-metal capacitor. W × L is the top plate; the capacitance is the film's ε·W·L/t with the plates' edge fringing, the series resistance comes from both plates' metal, the loss from the film's loss tangent, and the bottom plate's capacitance through the substrate to ground is included. Terminal 1 is the top plate and terminal 2 the bottom plate: for a shunt capacitor, ground terminal 2, which shorts that substrate capacitance out.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the top plate and terminal 2 the bottom plate, the one lying on the substrate, which carries the plate's capacitance to ground. For a shunt capacitor ground terminal 2.

Spiral Inductor (SPIRAL)

A square spiral of N turns, W wide with S between turns and a clear opening Din across the middle. Terminal 1 is the outer end; terminal 2 is the inner end, brought out over the turns on the air-bridge metal.

The nets of an instance line, in this order. Not interchangeable in the drawn part: terminal 1 is the outer end and terminal 2 the inner end, brought out over the turns on the bridge metal. The model itself is symmetric.

Octagonal Spiral Inductor (OSPIRAL)

The square spiral with its corners cut: the same N, W, S and Din, meaning the same things, with Din measured across the innermost pair of parallel flats. Every side is a constant S from the turn beside it, diagonals included. For the same footprint the winding is shorter than a square one's, which costs some inductance and saves more resistance. Its corners are 45° rather than 90°, which spreads the current that crowds into a square spiral's corners. N counts from the inner end, at the middle of the innermost flat, and the layout draws whole eighth turns.

The inductance is the same estimate as the square spiral's, summed over the octagonal coil as drawn. Extract the drawn coil for a value to rely on: circuitrf em <workspace> --component "OSPIRAL N=2.5 W=10 um S=10 um Din=100 um" -o L1.s2p.

The nets of an instance line, in this order. Not interchangeable in the drawn part: terminal 1 is the outer end and terminal 2 the inner end, brought out over the turns on the bridge metal. The model itself is symmetric.

Thin-Film Resistor (TFR)

The technology's resistor film as a serpentine: N parallel segments of width W and length L, joined by orthogonal links whose clear length between the segments is Lc. An N of 1 is a straight film with its contacts L apart. An odd N leaves the two ends on opposite sides, and an even N on the same side.

Its resistance is the film's sheet resistance times its squares: the straight film between the bends, plus 0.559 of a square for each corner. The contacts are not included.

Film chooses among the technology's resistive films, and it decides both the sheet resistance and the contact. Each row of the combobox says what it gives. On a level with metal the part draws contacts lapping the film's ends, and L runs between their edges. On a film level it draws a head on the metal at the contact via's far end with a via inside it, and L runs between the vias' inner edges. Left at its default it is the first film in the stackup. A name that matches no film is a refusal listing the real ones, in the dialog, in check and in a run.

The nets of an instance line, in this order. Interchangeable: the two ends of the film.

Air Bridge (AIRBRIDGE)

A span of the air-bridge metal crossing another line: L is the clear span between its two posts, W its width and Wu the width of the line it crosses. Terminals 1 and 2 are the landings; terminals 3 and 4 are the two ends of the crossed line's segment under the bridge, which is two bridge widths long. The two are coupled through the overlap capacitance. Tie terminals 3 and 4 to ground for a bridge over a ground strap.

The nets of an instance line, in this order. Terminals 1 and 2 are the bridge's two landings, and 3 and 4 the two ends of the line it crosses; each pair is interchangeable. Tie 3 and 4 to ground for a bridge over a ground strap.

Data-file components

EM Field Data

A finished EM run as a block: one parameter, File, a result record (.cemr). Its pins are named after the run's ports, in the run's order, and it stamps the record's Touchstone exactly as an SnP does, so its S is the file's. It holds a far field or a field set or it is refused, and it is the block a Fields analysis names. A result with neither belongs in an SnP.

EmFieldData:EM1 feed cl cr ct File="results/Loop Coil CoSim.openems.cemr"

Touchstone N-Port (SnP)

An N-port backed by a Touchstone (.sNp) file — measured or modelled S-parameters embedded in the circuit and interpolated onto the analysis sweep.

• NumPorts — the port count. Hidden; it drives the symbol and the pin count.
• File — the path to the Touchstone file. Once a file is chosen and is there, Preview opens it in the S-Parameter Viewer.
• RefNode — when true, expose a floating common reference pin (N+1 nets) instead of grounding each port.
• PinConfig and Pitch — the pin arrangement and spacing on the symbol.
• InterpMode, InterpDomain and ExtrapMode — how the data is interpolated between points, in which domain, and what happens beyond its frequency range.
• SdB_<i>_<j> and Sdeg_<i>_<j> — an offset on one S-parameter: SdB_3_1=0.2 dB raises |S31| by 0.2 dB, Sdeg_3_1=5 turns it by 5°, the same at every frequency. Ports are numbered from 1 and always separated by _ (SdB_10_1). Both are 0 unless set, which is what lets a sensitivity run rank an S-parameter and a Monte Carlo give it a tolerance. Because an offset is the same at every frequency it is not tuned or optimized. At 0 Hz only the dB offset applies.
• Reciprocal — auto (the default), tied or untied. Tied, one offset on S31 moves S13 with it, and only the lower entries (SdB_3_1, never SdB_1_3) are offered; untied, every entry has its own. auto ties a file whose S(i,j) and S(j,i) agree (every passive file does) and unties one that does not (an amplifier).

Noise. In an S-parameter run with Noise=yes, a two-port file's Touchstone noise block makes the block noisy by that data. The data is linear between rows, and the end rows are held outside them, with a warning. A passive file with no noise block is thermal at the block's own Temp (°C), or Dtemp above the ambient, or else the design's ambient. A file with gain and no noise block is taken as noiseless and named in the run's warning, and so is every Deembed. Noise=no makes the block noiseless whatever its file says (Switching a part's noise off).

When the file's header names its ports (! Port[1] = P1, which every EM result circuitRF writes carries), each lead shows its port's name in place of its number, shortened past eight characters. The pins are still ports 1…N: only the text beside them changes.

The symbol is dynamic; the pin arrangement, the pitch and the floating-reference option are covered in Dynamic symbols.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2.

Deembed

The opposite of an SnP. It reads a Touchstone file the same way and has the same parameters, but instead of adding the file's network to the circuit it removes it: it is the network that, cascaded with the file's, gives a plain connection.

Wire it as you would wire the SnP that adds the network. Ports 1…N/2 are one side, N/2+1…N the other, as in the file. Draw the chain that would put the fixture in, then swap the SnP for a Deembed and the part for the measurement:

Port:P1  p1 0 Num=1 Z=50 Ohm
SnP:A    p1 x  File="fixture_A.s2p" NumPorts=2      ; adds fixture A: what an instrument sees
SnP:DUT  x  p2 File="part.s2p"      NumPorts=2

Port:P1  p1 0 Num=1 Z=50 Ohm
Deembed:DA p1 x File="fixture_A.s2p" NumPorts=2      ; removes it again
SnP:M      x  y File="measured.s2p"  NumPorts=2
Deembed:DB y  p2 File="fixture_B.s2p" NumPorts=2     ; and fixture B on the other side

• Fixture files from your measurements. A TRL Calibration turns measured Thru, Reflect and Line standards into the two fixture files a pair of Deembeds takes off.
• Any even number of ports. A six-port that sits between a transistor's outer and inner gate, drain and source terminals de-embeds the transistor to its inner terminals. An odd count is refused when the netlist is read.
• An SnP and a Deembed on the same file cancel, at every frequency of the sweep, not only the file's own points, because both read it through the same interpolation with the same InterpMode, InterpDomain and ExtrapMode. Below and above the file's band both hold its end values, or both extrapolate, so they still cancel.
• It works in every analysis an SnP works in: DC (at 0 Hz), S-parameters, harmonic balance at every harmonic, loadpull, sweeps, tuning and optimization. In an envelope run it is not fitted as an SnP is: it undoes a network, so it would have to advance what that network delays, which no causal model can. It is approximated around each harmonic instead, and the run says so.
• It has gain. The network that undoes a lossy one has gain wherever that one has loss, so a stability run with NDF=yes refuses it by name.
• Where it cannot be built, the run stops and says where. A fixture that does not pass from one side to the other at some frequency has nothing to undo there: a series capacitor at 0 Hz is the usual case, and the message names the instance and the frequency. Apply bias outside the part being de-embedded, or use a file whose lowest frequency still passes through.
• A path through the network needs a net at each end. Pins k and N/2+k are the two ends of one path. Put both on ground and the current leaving one is no longer the current entering the other, so that path is not removed: for a FET's six-port, the outer source (pin 3) goes to ground and the inner source (pin 6) to the device's source, on a net of its own. A run with both ends of a path on ground warns, naming the pins.
• It takes no SdB_<i>_<j>, Sdeg_<i>_<j> or Reciprocal; set an offset on the SnP whose network it removes.

In the schematic it is in the palette under Data Files, and it is placed, pointed at a file and laid out exactly as an SnP is: Browse… sets the port count from the file, and a file with an odd number of ports is refused with a message. Its pins default to SplitLR, ports 1…N/2 down the left and the rest down the right in order, so each port faces its partner on the other side. It is always drawn as its own box, marked S⁻¹.

The TRL and De-embedding example (File ▸ New ▸ Examples) uses it three ways: two fixtures off a filter, and a 6-port off a GaN FET to show its intrinsic Cgs, Cgd, gm and Rds flat with frequency.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2. Not interchangeable: terminals 1 to N/2 are one side of the network its file holds and N/2+1 to N the other, in the file's order. Wire it exactly as an SnP on the same file would be wired to ADD that network, then swap the SnP for the Deembed and the part for its measurement: a fixture's instrument side faces the port and its part side faces the measured block. An SnP and a Deembed on one file, joined side to side in either order, are a through connection.

SPICE Model or Subcircuit

A SPICE .model card or .subckt definition placed as a component and run from its own file. Nothing is copied: edit the file and the schematic follows it.

• File — the path to the SPICE file.
• Name — which definition in that file to run. A vendor file usually holds a part and every piece the part is built from, each of them a definition in its own right; leaving Name blank picks the highest-level one, the one nothing else in the file calls.
• PinConfig and Pitch — the pin arrangement and spacing, for a .subckt only. A .model card draws as the device itself, whose terminals are where that device's terminals are.
• Glyph — set on a part placed from a vendor part library: C or L for a two-terminal capacitor or inductor, which then draws as the ordinary capacitor or inductor symbol. It is stored on the instance, so the part still draws as what it is when its library is missing, marked Not Found.

Any parameter the chosen .subckt declares appears as an ordinary editable row below the panel, seeded at the definition's own default.

The symbol is dynamic and is generated from the file. A .model card circuitRF has a device for draws as that device — a diode card draws as a diode — so the schematic says which lead is which without anything being opened. A .subckt draws as a box carrying the definition's own port names. Until a file is chosen it draws as a generic two-port, which can be placed and wired first.

A model type circuitRF has no equivalent for is refused by name, in the parameter dialog at the moment the file is chosen and again at Run. Nothing is approximated: the nearest native device would simulate and be quantitatively wrong.

The nets of an instance line, in this order.

Impedance N-Port (Z)

An N-port defined by its impedance matrix Z[p,q]. NumPorts is the port count, hidden, and it drives the symbol and pin count. The symbol grows with the port count — see Dynamic symbols.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2.

Nonlinear devices

Symbolically-Defined Device (SDD)

A user-defined nonlinear device: you write each port current — and, optionally, each port charge — as an equation in the port voltages, and circuitRF differentiates it automatically for the solver. This is how the GaN FET model in the netlist example is defined. The symbol is dynamic; see Dynamic symbols.

• I[x,0] — the port-x current equation, seeded as a 50 Ω conductance. Weight 0 is the current itself.
• Q[x], I[x,w], H[w] — optional charge equations, higher weightings, and weighting functions.
• C[n] / Cport[n] — bind a control current _cn to another device's current.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2.

Junction Diode (Diode)

A junction diode: anode at the top, cathode at the bottom. Rs is a model parameter, not a separate placed resistor — when it is non-zero the elaborator mints the internal node itself, so the schematic shows one device either way.

The nets of an instance line, in this order. a is the anode and c the cathode; forward current flows a to c.

Noise. Shot noise 2q·|Id| across the junction, always on, since it is what a junction carrying current does; flicker noise Kf·|Id|^Af/f on the same junction when Kf is above zero; and thermal noise 4kT/Rs across the series resistance when there is one. The S-parameter noise analysis evaluates them at the DC operating point and the device's own temperature.

The FET family

Five native large-signal FET models, one per published drain-current law. They are five separate components rather than one component with a model selector, because they are not variants of one another: each has its own parameter set, and several reuse a spelling for a different quantity — the quadratic law's Beta is a transconductance parameter, while the cubic law's is a gate-voltage shift with drain bias. One kind with a selector would present the union of all five parameter sets and silently accept the wrong ones.

All five share one glyph and one three-pin geometry — gate left, drain top, source bottom. The topology genuinely is the same, and the type label below the symbol names the law. The glyph is the JFET's: a MESFET's or HEMT's Schottky gate is a junction made directly on the channel, not an insulated gate, so the gate arrow lands on one unbroken (depletion) channel bar — into it for n-channel, out of it for p-channel. The source is an ordinary pin: these are not hard-wired common-source.

What all five share

Terminals and ports. Three nets — gate drain source — mapped onto two ports: port 0 is (gate, source) and port 1 is (drain, source). So the first port voltage is Vgs and the second is Vds, which is the form every published FET equation is written in. Nothing has to be transposed to use a datasheet parameter set.

What is modelled. The drain current and both of its derivatives — gm = ∂Id/∂Vgs and gds = ∂Id/∂Vds — computed analytically rather than by finite differences, which matters inside a Newton loop precisely where the device is most nonlinear. On top of that: optional forward gate conduction, as an ordinary diode from gate to source (set by Is and N, off when Is is zero), and gate charge (below). Parameter temperature scaling is modelled through Temp and Tnom.

Cgs, Cgd and CapModel

Gate charge is selectable, because the published models disagree about it. It is a parameter rather than a per-model decision for exactly that reason: two authors implementing "the Curtice model" from the literature will not necessarily give it the same gate charge.

At CapModel = 2 the charge on each junction is the standard depletion form:

Q = Cj0·Vbi/(1 − M) · [ 1 − (1 − V/Vbi)^(1 − M) ]        for V < Fc·Vbi
                                                          continued by its TANGENT above Fc·Vbi

parameters:  Cgs, Cgd   zero-bias capacitances (Cj0 for the two junctions)
             Vbi        junction potential
             M          grading coefficient
             Fc         forward-bias changeover, as a fraction of Vbi

The tangent continuation above Fc·Vbi is not cosmetic: a hard clamp there would leave a kink in the Jacobian and stall Newton.

Which to pick. Use 1 when your parameter set was extracted with fixed capacitances — which is the common case for the older laws — and when you want the cheapest evaluation. Use 2 when the extraction gives you junction parameters (Cj0, Vbi, M) and the gate swing is large enough for the bias dependence to matter, which in a power amplifier driven into compression it usually is.

Curtice quadratic (FET_Curtice)

The Curtice quadratic law: Vto, Beta, Alpha and Lambda.

The nets of an instance line, in this order.

Curtice–Ettenberg cubic (FET_CurticeCubic)

The Curtice–Ettenberg cubic law: A0–A3, Gamma, Beta and Vds0.

The nets of an instance line, in this order.

Statz (FET_Statz)

The Statz law: Vto, Beta, B, Alpha and Lambda.

The nets of an instance line, in this order.

Materka–Kacprzak (FET_Materka)

The Materka–Kacprzak law: Idss, Vp0, Gamma and Alpha.

The nets of an instance line, in this order.

Angelov / Chalmers (FET_Angelov)

The Angelov (Chalmers) law: Ipk, Vpk, P1–P3, Alpha and Lambda.

The nets of an instance line, in this order.

p-channel: Curtice-P, Statz-P, Materka-P

Three of the five laws are also offered as p-channel parts. Polarity is a sign, not a law: every voltage, current and charge is mirrored, so a p-channel tile is its n-channel counterpart with the same parameter list and the same equations. Vto (or Vp0) is stated the way a card states it — positive for a p-channel depletion MESFET — and circuitRF applies the sign itself.

Curtice-P (PFET_Curtice)

The nets of an instance line, in this order.

Statz-P (PFET_Statz)

The nets of an instance line, in this order.