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Components

Every component in the standard library — its symbol, what it does, and its parameters.

Symbols are rendered from the live drawing engine, with their connection leads and their pins shown unconnected — the component as you meet it in the palette, before anything is wired to it. Parameter tables are read from the component registry, so the defaults, units and on-schematic visibility below are the as-placed values by construction rather than by transcription.

Lumped elements

Resistor (R)

An ideal, frequency-independent resistor. R is the resistance.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Inductor (L)

An ideal inductor. L is the inductance. Couple two inductors with a Mutual element.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Capacitor (C)

An ideal, linear capacitor. C is the capacitance. For a voltage-dependent capacitance, see NonlinearC.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Series RLC (SRLC)

A resistance, an inductance and a capacitance in series, as one part. R, L and C are the three values; the branch impedance is R + jωL + 1/(jωC).

This is the shape a real capacitor takes above a few hundred megahertz, which is the usual reason to place one: a ceramic capacitor's datasheet gives an ESR and an ESL, and those go straight into R and L. The part is series-resonant at 1/(2π√(LC)), where its impedance falls to R — below that frequency it behaves as a capacitor, above it as an inductor. At DC the series capacitance makes the branch an open circuit.

Its pins sit exactly where a plain R, L or C's do, so you can swap one in for another without moving any wires. Its inductance can be coupled with a Mutual, which names the SRLC instance in place of an inductor.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Parallel RLC (PRLC)

The same three values in parallel — a tank. R, L and C all sit across the same two nodes, giving an admittance of 1/R + jωC + 1/(jωL).

At the parallel resonance 1/(2π√(LC)) the reactive parts cancel and the part is purely resistive at R, which is what makes it the natural way to enter a measured resonance: R sets the peak impedance, L and C set where it sits and how sharp it is. At DC the ideal inductor shorts it out.

Pin positions and Mutual coupling work exactly as they do for the SRLC above.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Series RL (SRL)

A resistance and an inductance in series, as one part: R + jωL. A real inductor, whose winding resistance is the R — and, unlike the SRLC you would otherwise place for the same job, with no third value on the schematic that nobody meant.

There is no series capacitance, so this branch does not open at DC: at ω = 0 it is simply R, which is what the physical part measures. Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Series RC (SRC)

A resistance and a capacitance in series: R + 1/(jωC). A real capacitor entered with its ESR, or a series RC damper across a resonance. At DC the capacitance makes the branch an open circuit.

It carries no inductor, so a Mutual naming one is refused rather than coupled — the refusal says so and names the part.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Series LC (SLC)

An inductance and a capacitance in series: jωL + 1/(jωC). The lossless series trap — its impedance falls to zero at 1/(2π√(LC)), which in a shunt arm is a notch. Below the resonance it behaves as a capacitor and above it as an inductor; at DC it is an open circuit.

Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Parallel RL (PRL)

A resistance and an inductance in parallel: an admittance of 1/R + 1/(jωL). The shunt form of a lossy coil, and the usual way a damped choke is entered. At DC the ideal inductor shorts it out.

Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Parallel RC (PRC)

A resistance and a capacitance in parallel: an admittance of 1/R + jωC. A leaky capacitor, or the shunt RC an equivalent circuit puts across a port. At DC the capacitor is an open and the part is R.

This is the one member of the RLC family that adds no branch current to the matrix — and therefore the one a Mutual cannot name.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Parallel LC (PLC)

An inductance and a capacitance in parallel: an admittance of jωC + 1/(jωL). The lossless tank — its impedance goes to infinity at 1/(2π√(LC)). For a tank with a finite peak impedance, use a PRLC and let R set the peak. At DC the ideal inductor shorts it out.

Its inductance can be coupled with a Mutual.

The nets of an instance line, in this order. Interchangeable on its own — but NOT once coupled. A Mutual (M) couples the two elements' branch currents, and each branch current runs from that element's own terminal 1 to its terminal 2, so swapping one of them reverses the sign of the coupling. Terminal 1 is the dotted end.

Ferrite Bead (Bead)

A two-terminal linear element: Rdc in series with a parallel L / Rp / Cp tank.

A bead is not an inductor and not a series RLC. The number a data sheet gives — "600 Ω at 100 MHz" — is an impedance, and the whole point of the part is that most of it is resistive at the frequency it is quoted at. That is what makes a bead absorb rather than reflect, and why it damps a supply rail where an inductor of the same reactance would ring against the decoupling capacitance. An inductor's loss is zero and a series RLC's is a constant R; a bead's rises from nothing at DC to a maximum at its ferromagnetic resonance and falls again above it.

Each element stands for a real mechanism:

Zero means not modelled for each of the three parallel elements, never "a short" or "a zero-ohm resistor". Rp = 0 removes the loss branch and leaves an ideal L; Cp = 0 removes the capacitive branch and the impedance goes on rising; L = 0 leaves a plain Rdc.

At DC the bead is Rdc and nothing else, because the inductive branch shorts the tank out. That is both the physics and what a DC operating point needs from this part — a bead in a supply rail must not open it.

The nets of an instance line, in this order. The two terminals are interchangeable — swapping them gives the same circuit.

Nonlinear Capacitor (NonlinearC)

A capacitor whose capacitance varies with voltage, C(V), modelled as a polynomial (Taylor) series. Enter the coefficients directly, or generate them from a C–V curve with the C–V Editor. C0 is the constant term; C1, C2, … are the higher-order coefficients, added in the editor or generated by the C–V Editor. Full treatment: The Nonlinear Capacitor & the C–V Editor.

The nets of an instance line, in this order. C(V) is evaluated at V(terminal 1) − V(terminal 2), so any odd coefficient (C1, C3, …) makes the two terminals distinct. With C0 alone the capacitor is linear and they are interchangeable.

Mutual Inductance (M)

Couples two existing inductors — named by instance — with a mutual inductance, the basis for transformers and coupled resonators. It has no pins of its own; Inductor1 and Inductor2 are the instance names of the two coupled inductors and M is the mutual inductance between them.

Either name may be any part that carries an inductor: an L, an SRLC, a PRLC, an SRL, an SLC, a PRL or a PLC — every one of them holds its inductor current on a branch the coupling can act on, and every one spells its value L. Naming anything else — an SRC or a PRC included, since neither has an inductor — is reported as an error when the design is elaborated.

No terminals — this component connects to nothing on the canvas.

Matching Network (Match)

A synthesised bandpass matching network placed as a single two-pin component, ground being the common return. Its whole design rides in a hidden Design parameter, so what it stamps is a property of the design rather than of the component type: the ladder it contains is the synthesised one minus whatever the two external terminations already supply, since absorbing those reactances is the point. Edit it in the Match Designer.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the R1 side and terminal 2 the R2 side. The synthesised ladder is stored R1-first, so swapping the two reverses every asymmetric match.

Sources

DC Voltage Source (Vdc)

A fixed DC voltage — gate and drain bias supplies. Vdc is the voltage.

The nets of an instance line, in this order. Vdc is the voltage at + relative to −.

Tone Source (VTone)

A single-tone (sinusoidal) voltage source for harmonic balance, with an optional DC offset. V is the tone amplitude, Freq the tone frequency, and Vdc a DC offset.

The nets of an instance line, in this order. V and Vdc are the voltage at + relative to −, and Phase is referred to the same pair.

Current Tone Source (ITone)

The current-source dual of VTone — a single-tone sinusoidal current source with an optional DC offset. I is the tone amplitude, Freq the tone frequency, and Idc a DC offset. Use it to drive a node with a known current rather than a known voltage: an ideal current source has infinite output impedance, so it sets the current through a branch and lets the network decide the voltage.

The arrow says which way the current goes. A positive I delivers current into pin 1 (the arrowhead end, the top pin as drawn) and draws it out of pin 2. Note this is the opposite of the SPICE I element, which sinks current from its first node; circuitRF uses one direction convention for every source it has, and the glyph states it so you never have to remember which.

Like VTone, the + button in the parameter editor turns it into a multi-tone source: the scalar I/Freq migrate to I[1]/Freq[1] and each further tone gets its own Freq[n], I[n] and Phase[n].

The nets of an instance line, in this order. A positive I is delivered INTO the + terminal and drawn out of the −, which is what the arrow on the + lead points at. Note this is the opposite sense to the VCCS's arrow, which is a controlled source and is drawn the way controlled sources are.

RF Power Source (P1Tone)

An RF source specified by available power with an internal source impedance — the natural drive for power-amplifier and loadpull work. It can also serve as an S-parameter port (via Num), and accepts per-harmonic source terminations Z[k] for harmonic source-pull.

• Num — S-parameter port index, sharing one pool with Term.
• Pavl — available power.
• Z — fundamental source impedance; Freq — fundamental frequency; Phase — phase.
• Z[k] — per-harmonic source termination: Z[0] is baseband/DC, Z[2] the second harmonic, and so on. Added in the parameter editor.

The nets of an instance line, in this order. + is the RF output and − the reference, normally ground — Term's own convention, since this is a source with Term's internal resistance in front of it. The source's internal impedance Z is in series with +.

Multi-Tone RF Power Source (PnTone)

The multi-tone sibling of P1Tone — an available-power RF source that injects several carriers at once from a single component, the natural drive for two-tone intermodulation work. A freshly placed PnTone is already a two-tone source (tones 1 and 2, at 1.99 and 2.01 GHz); the + and − buttons in the editor add and remove tones. Each tone has its own Freq[i], Pavl[i] and Phase[i]; all tones share one source impedance Z and the same per-band terminations Z[k], where each mixing product is terminated by the band its frequency falls in.

Unlike P1Tone, PnTone is not an S-parameter port — it has no Num. The tones a PnTone drives must match the tones declared on the Harmonic Balance analysis: the analysis owns the mixing grid, and the source just supplies power at those frequencies.

The nets of an instance line, in this order. + is the RF output and − the reference, normally ground — Term's own convention, since this is a source with Term's internal resistance in front of it. The source's internal impedance Z is in series with +.

Voltage-Controlled Current Source (VCCS)

An ideal transconductance: the current it delivers is G times the voltage across a separate, purely-sensing control pair.

I = G · (V(ctrl+) − V(ctrl−))

Four terminals in two pairs — the output pair (out+ top, out− bottom) carries the current, and the control pair (ctrl+, ctrl−, on the left) senses the controlling voltage. The control pair draws no current at all, which is what makes the source ideal and what makes the device unilateral: nothing travels backwards through it. G is the transconductance, in siemens.

The arrow says which way the current goes, and it points down: a positive G and a positive control voltage draw current in at out+ and out at out−. That is the SPICE G element's own direction, and the way a small-signal transconductance is drawn in a device model — the controlled source sinks drain current from the drain node. So a VCCS across a grounded load resistor is inverting, and a 50 Ω, G = 10 mS stage measures S21 = −0.25.

Note the VCCS's arrow points the opposite way to ITone's. That is not an inconsistency to squint past: ITone is an independent source and delivers current to its arrow pin, while the VCCS is a controlled source drawn the way controlled sources are drawn. Read each symbol's own arrow.

The nets of an instance line, in this order.

Voltage-Controlled Voltage Source (VCVS)

An ideal voltage gain: the voltage it holds across its output pair is E times the voltage across a separate, purely-sensing control pair.

V(out+) − V(out−) = E · (V(ctrl+) − V(ctrl−))

Four terminals in two pairs, laid out exactly as the VCCS's are — the output pair (out+ top, out− bottom) and the control pair (ctrl+, ctrl−, on the left), which draws no current at all. E is a voltage ratio and carries no unit.

The two tiles differ in one thing: what the diamond carries. The VCCS's arrow points at the current it delivers; the VCVS has a ± pair down its axis instead, because there is no current direction to point at. A VCVS states a potential difference and whatever current the rest of the circuit draws through it flows — including none, if nothing is connected across the output pair. That is the ideal source's own behaviour, not a limitation.

Being ideal, its output impedance is zero: it holds E times the control voltage no matter what it is loaded with. Put a series resistor after it if you want a source with an impedance.

The nets of an instance line, in this order.

Terminals & ports

Ground (GND)

The global reference node (net 0). No parameters.

Term

An S-parameter port: a numbered, reference-impedance termination where the simulator excites and measures. Num is the port index, auto-assigned at placement; Z is the reference impedance. See Pins, Ports & Terms for how it differs from a Pin.

The nets of an instance line, in this order.

Grounded Term (TermG)

A Term whose second port is permanently grounded, presenting as a one-port. It is a packaging convenience rather than a parallel model: it uses Term's own engine component and glyph exactly, with the ground symbol drawn at Term's port-2 location, so a schematic that swaps Term + GND for a TermG is electrically identical.

One terminal, + — an instance line writes a single net.

Pin

A cell's interface terminal — connectivity only, no electrical model. Pins on a cell's symbol are how the cell connects to the parent that instances it. Num is the interface port index, auto-assigned; Name is an optional label, and extraction uses P{Num} when it is blank. An optional Polarity of Plus or Minus, set in the editor, forms a differential pair sharing one Num.

One terminal, 1 — an instance line writes a single net.

Current Probe (IProbe)

A 0 V series ammeter placed in a branch to read its current. Its instance name — Iout, say — is how measurements reference that current: I("Iout", 1). No parameters.

The nets of an instance line, in this order. A 0 V ammeter: the current it reports flows np to nm. Swapping the two negates every measurement that reads it.

No parameters.

Voltage Probe (VProbe)

A one-terminal voltage probe. Drop it anywhere on a wire and that net is reported under the probe's instance name — Vout, say. That name is what the trace picker lists and what a measurement expression reads: V("Vout").

It is a label, not a part. It has one terminal, so it cannot bridge two nets; the elaborator builds no model for it, so it stamps nothing; and a design simulates identically with every VProbe deleted. Placing one can never change an answer — it can only add a name to it.

On an unnamed wire the probe's name becomes the net's name. There is one row in the results, called Vout, and no n7 beside it — the automatic name was never a name anyone chose, and two rows for one point in the circuit is one row too many.

On a wire you have already labelled, both names appear. The label is not overwritten: a wire labelled n_drain with a Vout probe on it shows up twice — as n_drain and as Vout — carrying the same voltage. The probe is an alias there, and either name plots and measures the same node.

Two rules keep the names unambiguous, and breaking either refuses the run rather than reporting:

• Two VProbes may not share a name.
• A VProbe may not share a name with a net.

A VProbe that touches nothing is reported in the Messages panel and drops out of the results, rather than reporting a plausible number for a point you never probed. So is one placed on ground, which is 0 V by definition.

It is the one component you can drag off a wire. Every other symbol takes its wires with it when you move it, because moving the picture must never re-wire the circuit. A probe has nothing to re-wire, so dragging it leaves the drawing exactly as it was and puts the probe wherever you dropped it — pick it up, look somewhere else, run again, with no repair work in between. Rotating it behaves the same way, and a wire dragged out from under a probe simply leaves it behind.

Select the probe and its wire together and they move as one, so the probe stays on the net.

One terminal, v — an instance line writes a single net. One terminal, at the arrow's tip. It taps the net it touches and names it after the instance; there is no second terminal to get the wrong way round, and nothing it can short together.

No parameters.

Stability Probe (WSProbe)

A stability probe, placed in a node so that it splits the node into a generator-side terminal (G) and a load-side terminal (L). It implements T. A. Winslow, General Circuit Analysis Using The WSProbe (2023); every quantity below is that document's, under its own name.

Electrically it is an IProbe — a 0 V short — and it is placed the same way: drop it onto the wire whose node you want to look at, and circuitRF deletes the stretch of wire between its two pins so the probe breaks into the run instead of being shorted by it. It perturbs nothing, so a design simulates identically with every WSProbe deleted. It takes no parameters.

The letters are the orientation. G is the generator-side terminal and L the load-side one: ZG looks out of G, ZL out of L. Rotating or mirroring the symbol moves the drawing and never the pin order, so swapping the two means swapping the wires — which swaps every G/L-labelled output and negates nothing else.

What it produces is not a number but a matrix. An S-parameter run with any WSProbe in it writes a wsp cube — 2N x 2N for N probes — and six named outputs per probe: H0 and Y0, the driving-point impedance and admittance; ZG and ZL, the bidirectional impedances; LG, the bilateral loop gain; and F = 1 - LG. Two stability margins, SM_Y0 and SM_H0, come with them. Everything else the document derives — every other loop gain, the reduced two-port at the probe, the probe-pair blocks, the global loop gains over a set of probes — is post-processing of that one matrix, and is available in the Data Display's trace card and in a measure line.

Reading a node for stability is two plots, not one. Plot 1/H0 and 1/Y0 on a polar chart and look for a clockwise crossing of the negative real axis; the trace card reports the frequencies it finds, or none. Both must be checked, because a zero can hide the pole in one of them but never in both — a series resonance shows in 1/Y0 alone and a parallel one in 1/H0 alone.

The stability margin is a distance, and the search is the detector. SM_Y0 and SM_H0 are unitless numbers in [0, 1], shown in dB (20*log10), and the trace card prints each one's minimum beside the crossing search that pairs with it. A node with positive resistance on both sides can never read below -12 dB, so anything under that line certifies negative resistance on one side; the run reports any probe whose margin falls below the analysis' MarginThreshold (default -15 dB) as worth looking at. That report is a note, not a warning: a low margin is somewhere to look, not a failure.

The WSProbe has its own chapter — every quantity with its equation, the probe pairs, the global loop gains, the stability envelope, the probe under harmonic balance, the NDF, and an appendix on stability analysis itself.

The nets of an instance line, in this order. G is the generator-side terminal, L the load-side. ZG looks out of G, ZL out of L; swapping them swaps every G/L-labelled output and negates nothing else.

No parameters.

Tuner / SourceTuner / LoadTuner

A programmable RF termination. The three variants are the same engine component with different glyphs and net ordering — match the symbol to its role. SourceTuner sits on the source side, LoadTuner on the load side.

• Z[1] — the fundamental termination. Required, and it accepts complex literals such as 50+j*10. Add Z[2], … in the editor, or G[k] to give a reflection coefficient instead.
• Zdefault — the catch-all termination for harmonics not otherwise specified, and the impedance the tuner presents at DC.
• Z0 — the reference impedance for any G[k] entry.
• BiasTee — on or off, chosen from a picker. on builds the internal bias-tee and DC supply, which the loadpull directive requires. With it off the tuner is RF-only: there is no DC path through it to the reference node.
• Vbias — the DC bias at the DUT-facing port when the bias-tee is on.
• ShowBias — true or false, chosen from a picker. Display only: it draws the bias-tee on the glyph and never reaches the engine, so the extracted netlist is identical either way.

One terminal, 1 — an instance line writes a single net.

Which analyses a tuner works in

All five that terminate a circuit: DC, S-parameters, harmonic balance, loadpull and loadpull pursuit. It is an ordinary linear component, so a parametric sweep wrapping any of them sweeps it like anything else.

How its frequency response is defined

A tuner is not a fitted network. It presents the impedance you declared, exactly, with no interpolation between entries and no roll-off. Which entry it presents depends on the analysis:

So the answer to "what does Z[2] do in an S-parameter run?" is nothing: declare the band you care about in Z[1], and use several S-parameter analyses if you want several terminations.

In loadpull and pursuit, the SourceTuner is also the RF generator

A loadpull run needs a drive as well as terminations, and the SourceTuner supplies it: the loadpull and pursuit engines assign it the source role, which stamps a single-tone RF generator inside it, behind the impedance it presents. The generator is calibrated to available power — |V_s| = √(8·P_avl·Re Z₁) — so the power you ask for and the impedance the DUT is driven from stay consistent as either one moves across the sweep.

The drive level is not a tuner parameter. There is no Pavl row on the component, because the sweep over drive belongs to the run, not to the part. The ladder is set in the analysis: Pin start (dBm), Pin max (dBm) and Pin step (dB) in the Loadpull and Loadpull Pursuit setup, walked upward from the start until compression is reached or the cap stops it.

Transmission lines

Ideal Transmission Line (TLIN)

An ideal, lossless transmission line specified by characteristic impedance Z and electrical length E at a reference frequency F.

The nets of an instance line, in this order. The two terminals are interchangeable: the line is uniform, so neither end is the input.

Microstrip Line (MLIN)

A physical microstrip line on the current technology's substrate: W is the conductor width and L the length. Unlike TLIN, its impedance and loss follow from the geometry and the substrate rather than being stated.

The nets of an instance line, in this order. The two terminals are interchangeable: the line is uniform, so neither end is the input.

Microstrip Bend (MBEND)

A right-angle microstrip bend of width W, optionally mitred, modelled with its discontinuity rather than as an ideal corner.

The nets of an instance line, in this order. The two terminals are interchangeable. One width and one angle describe the whole bend, so the pins differ only in which way it turns on the canvas.

Microstrip T-Junction (MTEE)

A three-port microstrip T-junction. W1, W2 and W3 are the widths of the three arms.

The nets of an instance line, in this order.

Microstrip Cross-Junction (MCROSS)

A four-port microstrip cross-junction, with a width per arm.

The nets of an instance line, in this order.

Linear Microstrip Taper (MTAPER)

A linearly tapered microstrip line running from width W1 to width W2 over length L.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the W1 end and terminal 2 the W2 end.

Klopfenstein Taper (MKLOPF)

A Klopfenstein-taper microstrip line — the taper profile that gives the shortest line for a stated in-band ripple. Specify the two impedances (or the two widths), the maximum reflection GammaMax, and either a length or a 3 dB corner frequency.

The nets of an instance line, in this order. Not interchangeable: terminal 1 is the Z1 end and terminal 2 the Z2 end.

Wirebond (wBond)

A wirebond design placed as a single component. Its symbol is generated from the design it carries — two pins per wire array plus a REF pin — so both the pin count and the pin names are properties of that design rather than of the component type. The wires themselves are drawn in the layout view, not here.

Terminals are set by Arrays; this component has no fixed pin geometry of its own.

Data-file components

Touchstone N-Port (SnP)

An N-port backed by a Touchstone (.sNp) file — measured or modelled S-parameters embedded in the circuit and interpolated onto the analysis sweep.

• NumPorts — the port count. Hidden; it drives the symbol and the pin count.
• File — the path to the Touchstone file.
• RefNode — when true, expose a floating common reference pin (N+1 nets) instead of grounding each port.
• PinConfig and Pitch — the pin arrangement and spacing on the symbol.
• InterpMode, InterpDomain and ExtrapMode — how the data is interpolated between points, in which domain, and what happens beyond its frequency range.

The symbol is dynamic; the pin arrangement, the pitch and the floating-reference option are covered in Dynamic symbols.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2.

SPICE Model or Subcircuit

A SPICE .model card or .subckt definition placed as a component and run from its own file. Nothing is copied: edit the file and the schematic follows it.

• File — the path to the SPICE file.
• Name — which definition in that file to run. A vendor file usually holds a part and every piece the part is built from, each of them a definition in its own right; leaving Name blank picks the highest-level one, the one nothing else in the file calls.
• PinConfig and Pitch — the pin arrangement and spacing, for a .subckt only. A .model card draws as the device itself, whose terminals are where that device's terminals are.

Any parameter the chosen .subckt declares appears as an ordinary editable row below the panel, seeded at the definition's own default.

The symbol is dynamic and is generated from the file. A .model card circuitRF has a device for draws as that device — a diode card draws as a diode — so the schematic says which lead is which without anything being opened. A .subckt draws as a box carrying the definition's own port names. Until a file is chosen it draws as a generic two-port, which can be placed and wired first.

A model type circuitRF has no equivalent for is refused by name, in the parameter dialog at the moment the file is chosen and again at Run. Nothing is approximated: the nearest native device would simulate and be quantitatively wrong.

The nets of an instance line, in this order.

Impedance N-Port (Z)

An N-port defined by its impedance matrix Z[p,q]. NumPorts is the port count, hidden, and it drives the symbol and pin count. The symbol grows with the port count — see Dynamic symbols.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2.

Nonlinear devices

Symbolically-Defined Device (SDD)

A user-defined nonlinear device: you write each port current — and, optionally, each port charge — as an equation in the port voltages, and circuitRF differentiates it automatically for the solver. This is how the GaN FET model in the netlist example is defined. The symbol is dynamic; see Dynamic symbols.

• I[x,0] — the port-x current equation, seeded as a 50 Ω conductance. Weight 0 is the current itself.
• Q[x], I[x,w], H[w] — optional charge equations, higher weightings, and weighting functions.
• C[n] / Cport[n] — bind a control current _cn to another device's current.

The nets of an instance line, in this order. How many there are is set by NumPorts; the table shows NumPorts = 2.

Junction Diode (Diode)

A junction diode: anode at the top, cathode at the bottom. Rs is a model parameter, not a separate placed resistor — when it is non-zero the elaborator mints the internal node itself, so the schematic shows one device either way.

The nets of an instance line, in this order. a is the anode and c the cathode; forward current flows a to c.

The FET family

Five native large-signal FET models, one per published drain-current law. They are five separate components rather than one component with a model selector, because they are not variants of one another: each has its own parameter set, and several reuse a spelling for a different quantity — the quadratic law's Beta is a transconductance parameter, while the cubic law's is a gate-voltage shift with drain bias. One kind with a selector would present the union of all five parameter sets and silently accept the wrong ones.

All five share one glyph and one three-pin geometry — gate left, drain top, source bottom. The topology genuinely is the same, and the type label below the symbol names the law. The source is an ordinary pin: these are not hard-wired common-source.

What all five share

Terminals and ports. Three nets — gate drain source — mapped onto two ports: port 0 is (gate, source) and port 1 is (drain, source). So the first port voltage is Vgs and the second is Vds, which is the form every published FET equation is written in. Nothing has to be transposed to use a datasheet parameter set.

What is modelled. The drain current and both of its derivatives — gm = ∂Id/∂Vgs and gds = ∂Id/∂Vds — computed analytically rather than by finite differences, which matters inside a Newton loop precisely where the device is most nonlinear. On top of that: optional forward gate conduction, as an ordinary diode from gate to source (set by Is and N, off when Is is zero), and gate charge (below). Parameter temperature scaling is modelled through Temp and Tnom.

Cgs, Cgd and CapModel

Gate charge is selectable, because the published models disagree about it. It is a parameter rather than a per-model decision for exactly that reason: two authors implementing "the Curtice model" from the literature will not necessarily give it the same gate charge.

At CapModel = 2 the charge on each junction is the standard depletion form:

Q = Cj0·Vbi/(1 − M) · [ 1 − (1 − V/Vbi)^(1 − M) ]        for V < Fc·Vbi
                                                          continued by its TANGENT above Fc·Vbi

parameters:  Cgs, Cgd   zero-bias capacitances (Cj0 for the two junctions)
             Vbi        junction potential
             M          grading coefficient
             Fc         forward-bias changeover, as a fraction of Vbi

The tangent continuation above Fc·Vbi is not cosmetic: a hard clamp there would leave a kink in the Jacobian and stall Newton.

Which to pick. Use 1 when your parameter set was extracted with fixed capacitances — which is the common case for the older laws — and when you want the cheapest evaluation. Use 2 when the extraction gives you junction parameters (Cj0, Vbi, M) and the gate swing is large enough for the bias dependence to matter, which in a power amplifier driven into compression it usually is.

Curtice quadratic (FET_Curtice)

The Curtice quadratic law: Vto, Beta, Alpha and Lambda.

The nets of an instance line, in this order.

Curtice–Ettenberg cubic (FET_CurticeCubic)

The Curtice–Ettenberg cubic law: A0–A3, Gamma, Beta and Vds0.

The nets of an instance line, in this order.

Statz (FET_Statz)

The Statz law: Vto, Beta, B, Alpha and Lambda.

The nets of an instance line, in this order.

Materka–Kacprzak (FET_Materka)

The Materka–Kacprzak law: Idss, Vp0, Gamma and Alpha.

The nets of an instance line, in this order.

Angelov / Chalmers (FET_Angelov)

The Angelov (Chalmers) law: Ipk, Vpk, P1–P3, Alpha and Lambda.

The nets of an instance line, in this order.

p-channel: Curtice-P, Statz-P, Materka-P

Three of the five laws are also offered as p-channel parts. Polarity is a sign, not a law: every voltage, current and charge is mirrored, so a p-channel tile is its n-channel counterpart with the same parameter list and the same equations. Vto (or Vp0) is stated the way a card states it — positive for a p-channel depletion MESFET — and circuitRF applies the sign itself.

Curtice-P (PFET_Curtice)

The nets of an instance line, in this order.

Statz-P (PFET_Statz)

The nets of an instance line, in this order.

Materka-P (PFET_Materka)

The nets of an instance line, in this order.

The junction FET

Two tiles — NJFET and PJFET — over the Shichman–Hodges square law, one set of equations with one sign changed.

Vgt = Vgs − Vto
Id  = 0                                            Vgt ≤ 0        cutoff
    = Beta·Vds·(2·Vgt − Vds)·(1 + Lambda·Vds)      Vds < Vgt      linear
    = Beta·Vgt²·(1 + Lambda·Vds)                   Vds ≥ Vgt      saturation

The gate is two junctions. Cgs and Cgd are the zero-bias capacitances of bias-dependent depletion charge, not fixed capacitors: Cgd falls as the gate-drain junction is reverse-biased, which at RF is most of the reverse isolation. Both junctions also conduct, with a diffusion term and an optional recombination term (Isr/Nr) that is a second exponential with its own ideality — folding it into the first would fit one decade of the gate leakage and miss the rest.

The device is symmetric, like the MOS transistor: which end acts as the drain is decided by the bias. Rd and Rs are model parameters, on internal nodes circuitRF mints, not resistors you place beside the device.

Vtotc shifts the pinch-off additively, in volts per degree; Betatce scales Beta in percent per degree — 1.01^(tc·ΔT), which is not the same as 1 + 0.01·tc·ΔT once ΔT is more than a few tens of degrees. The two forms are the published ones and they are not interchangeable.

n-channel (JFET_N)

The gate arrow points into the channel. The channel bar is unbroken — a depletion device, conducting at zero gate bias, which is the opposite of the MOS glyph's three segments.

The nets of an instance line, in this order.

p-channel (JFET_P)

The gate arrow points out of the channel. Same equations, every sign reversed — so Vto is positive, as a p-channel card states it.

The nets of an instance line, in this order.

The bipolar transistor

Two components — NPN and PNP — over one set of equations and one parameter list. This is the opposite arrangement from the FET family above, and for the opposite reason: there the five names denote five different drain-current laws, while here the parameter list is identical and only a sign differs. It is still two components rather than one with a polarity setting, because the two draw differently: the emitter arrow is the whole of what tells a reader which transistor is on the schematic, and a setting would leave the drawing and the netlist free to disagree.

Terminals. Three pins — collector top, base left, emitter bottom. The base is an ordinary pin and so is the emitter: these are not hard-wired to any configuration.

Rb, Re and Rc are model parameters, not separately placed resistors. When one of them is non-zero the elaborator mints the internal node itself, so the schematic shows one device either way. They are not optional detail at RF — Rb sets the input match and the noise, Re degenerates the transconductance, and all three are shunted by the junction capacitances — which is why the internal nodes are genuine unknowns rather than being folded away. Folding them would be exact at DC and wrong in harmonic balance, where an internal node carries its own harmonic content.

What is modelled

The standard charge-control model. Vt is kT/q at the device temperature; primed voltages are taken at the internal nodes, inside the parasitic resistances.

Icc  = Is·(exp(Vb'e'/(Nf·Vt)) − 1)                    forward transport
Iec  = Is·(exp(Vb'c'/(Nr·Vt)) − 1)                    reverse transport
Ibe  = Icc/Bf + Ise·(exp(Vb'e'/(Ne·Vt)) − 1)          base current, emitter junction
Ibc  = Iec/Br + Isc·(exp(Vb'c'/(Nc·Vt)) − 1)          base current, collector junction
Ict  = (Icc − Iec)/qb                                 collector-to-emitter transport

q1   = 1 / (1 − Vb'c'/Vaf − Vb'e'/Var)                base-width modulation (the Early effect)
q2   = Icc/Ikf + Iec/Ikr                              high-level injection
qb   = q1/2 · (1 + sqrt(1 + 4·q2))

Qbe  = Qj(Vb'e'; Cje,Vje,Mje) + Tff·Icc/qb            depletion + diffusion charge
Qbc  = Xcjc·Qj(Vb'c'; Cjc,Vjc,Mjc) + Tr·Iec
Tff  = Tf·(1 + Xtf·(Icc/(Icc+Itf))²·exp(Vb'c'/(1.44·Vtf)))

Every derivative of every one of those is computed analytically rather than by finite differences, which matters inside a Newton loop precisely where the device is most nonlinear.

The base resistance is current-dependent. With Irb given it follows the standard conductivity-modulation relation, falling from Rb at zero base current towards Rbm at high current; with Irb zero it follows Rbm + (Rb − Rbm)/qb instead, which is the same physics stated through the base charge. Both are in the published model, and which one applies is decided by the parameter set.

Xcjc splits the collector junction across the base resistance. That fraction of Cjc sits on the internal base node and the remainder runs from the external base to the internal collector — a real distributed effect, and the reason a device's feedback capacitance does not simply see Rb. When Rb is zero the two nodes are the same net and the halves add back to Cjc, so nothing special happens.

n-p-n (BJT_NPN)

The emitter arrow points out of the base — conventional current leaving the emitter.

The nets of an instance line, in this order.

p-n-p (BJT_PNP)

The emitter arrow points into the base. Same equations, same parameter names, every voltage and current negated — so a parameter set written for one polarity is used unchanged for the other.

The nets of an instance line, in this order.

The MOS transistor

Two tiles — NMOS1 and PMOS1 — over one set of equations with one sign changed, arranged like the bipolar pair rather than like the five FET laws. The 1 is the level: the Shichman–Hodges square law, the original compact MOSFET model and the one every later level is written as a departure from.

What is modelled

Vth  = Vto + Gamma·(√(Phi − Vbs) − √Phi)
Vgt  = Vgs − Vth
Id   = 0                                              Vgt ≤ 0        cutoff
     = Beta·(Vgt − Vds/2)·Vds·(1 + Lambda·Vds)        Vds < Vgt      linear
     = (Beta/2)·Vgt²·(1 + Lambda·Vds)                 Vds ≥ Vgt      saturation
Beta = Kp·W/Leff,   Leff = L − 2·Ld

The device is symmetric. Which terminal acts as the drain is decided by the bias, not by the schematic: drive Vds negative and circuitRF swaps the two ends and evaluates the law in the orientation it is published in. A model that did not would return a plausible, wrong current for every transmission gate and every passive mixer ever drawn.

Both bulk junctions are real diodes, with their own saturation currents, their own depletion charge and their own sidewall term. They are what makes the substrate connection matter, and they are why a bulk biased above the source or the drain draws enormous current — as it does in silicon.

Rd and Rs are model parameters, not resistors you place. A non-zero one moves the intrinsic transistor onto an internal node circuitRF mints for it, so the schematic shows one device either way. That node is a genuine unknown rather than something eliminated locally: at RF the ohmic resistances are shunted by the junction and overlap capacitances, and collapsing them is exact at DC and wrong in harmonic balance.

The gate charge

The intrinsic gate charge is the charge-based long-channel result, not the Meyer capacitance set that a transient simulator conventionally uses.

That difference matters here more than it does in a time-stepping simulator. Meyer's model states three capacitances that each depend on more than one terminal voltage, so the charge they imply depends on the path taken through the bias space — go once around a harmonic cycle and it does not return to where it started, and a periodic steady-state solve has nothing to converge to. Integrating the channel charge directly is conservative by construction, and its derivatives reduce to exactly Meyer's capacitances wherever Meyer's are right: Cox at Vds = 0, two thirds of Cox in saturation, zero in cutoff.

The channel charge is split evenly between the drain and the source. The alternative 40/60 split is the better one in a switching transient; at RF both ends see the same signal through the same channel resistance, and the even split is what keeps the device symmetric under the drain/source swap above.

n-channel (MOS1_N)

The bulk arrow points into the channel — the substrate junction read the usual way. The channel bar is drawn in three segments, the standard mark for an enhancement device: there is no channel until the gate makes one, so the part is off at zero gate bias.

The nets of an instance line, in this order.

p-channel (MOS1_P)

The bulk arrow points out of the channel. Same equations, same parameter names, every voltage, current and charge negated — so Vto is stated as the card states it, negative for an ordinary p-channel enhancement device, and circuitRF applies the sign itself.

The nets of an instance line, in this order.

Level 3: the short-channel law

NMOS3 and PMOS3 are the same four terminals and the same glyph over a different set of equations — the semi-empirical short-channel model. Two more tiles rather than a Level parameter on the level-1 ones, for the reason the five FET laws are five tiles: a level is a different law, and its six parameters mean nothing to the other one.

Each parameter turns on exactly one mechanism and each is off at zero, so a level-3 card stating two or three of them is an ordinary thing to import.

Subthreshold conduction (Nfs) and impact ionisation are still absent, exactly as at level 1. The current goes to zero at threshold in both.

n-channel (MOS3_N)

The nets of an instance line, in this order.

p-channel (MOS3_P)

The nets of an instance line, in this order.

The vertical power MOSFET

NVDMOS and PVDMOS — a separate component from the lateral MOS pair, not a setting of it. Three pins, not four: the source-to-body short is inside the silicon, and that is exactly what turns the substrate junction into a body diode between source and drain.

Three things a power MOSFET is chosen for are absent from the lateral model, and every one is what a user is asking about when they reach for this part.

The body diode is a component of the circuit, not a leakage path. It is the freewheeling diode of every half-bridge and the conduction path of every synchronous rectifier during dead time, and it carries the full load current there. So it has its own saturation current, its own reverse recovery charge (Tt) and its own avalanche breakdown (Bv) — a rated mode for this part, not a failure — and its current is reported on its own branch, I:M1:body.

The gate-drain capacitance collapses with drain bias, by one to two orders of magnitude. That collapse is the switching loss: the Miller plateau is the gate charge pouring into it while the drain swings. Cgdmax and Cgdmin are the two ends of a data sheet's reverse-transfer curve and Vgdt is how sharply it falls between them. A constant capacitance of either plateau value gets the switching time wrong by the ratio of the two.

The gate resistance Rg is in the drive path, in series with a capacitance that large, so it sets the switching speed as much as the drive current does.

n-channel (VDMOS_N)

The bulk arm turns and joins the source lead instead of leaving as a fourth pin — that is the source-to-body short — and the body diode is drawn explicitly on the right, conducting from source to drain.

The nets of an instance line, in this order.

p-channel (VDMOS_P)

The nets of an instance line, in this order.

The IGBT

NIGBT and PIGBT — an insulated-gate channel driving the base of a wide-base bipolar transistor. That structure is the model, and it is what gets the device's two defining behaviours right without either being fitted.