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The Stackup

The layers your board is actually made of — and, because it decides the ground plane, where the negative terminal of every EM port is.

Your layout is a set of flat shapes. The stackup is what turns those shapes into a physical structure: what each conductor is made of, how thick it is, what dielectric separates it from the next one, and — the part that catches people — which conductor is ground.

That last one is not a detail. An EM port has two terminals, and only one of them is anywhere near your artwork: the other is the ground plane. You do not set it per port. The stackup does, for every port in the run at once.

Where the stackup lives

The stackup is part of a technology — a .ctech file in the workspace's tech/ folder, edited in the technology editor's Stackup tab. It belongs to the technology rather than to a layout, because it describes a process: every board built on that process has the same layers, whatever is drawn on them.

A layout names a technology (or leaves the name blank to mean the workspace default). Everything else — the layer table, the DRC rules, the default display unit — lives in the same file. See The Layout Editor for the rest of it.

A missing technology does not block drawing, but it does block an EM run. Layers fall back to a generated palette and editing carries on; the EM run refuses rather than inventing a stackup, because there is no honest default for "how far above the ground plane is this trace".

Anatomy of a stackup

A stackup is an ordered list, top to bottom, of three kinds of entry, plus two boundary conditions for what is above and below the whole sandwich. Seen in cross-section, it is a sandwich:

That picture is in the application, and you edit it there

The cross-section above is not a diagram drawn for this page. It is the upper half of the Stackup tab, drawn from whichever .ctech you have open, and it is the main way to work on a stackup: the thing a list cannot tell you — which metal is on top, how thick the substrate is against the copper on it, which two conductors a via actually joins — is the thing a cross-section says at a glance.

The card list underneath it edits the same entries and always agrees with it. They are two views of one stackup, not two copies: whichever surface you change it on, the other follows immediately, the Undo and Redo buttons at the top of the window cover it, and the layouts you have open repaint against the changed technology without waiting for a save.

In roughly the order you will meet them:

The drawing scrolls when a stack is taller than its pane, and the divider between it and the cards drags. Neither pane can be dragged out of existence — to give one of them the whole tab, use the two small chevron toggles at the left of the summary row, which collapse the drawing and the card list respectively.

How tall each layer is drawn

Heights are relative within a kind and never across kinds. A conductor twice the thickness of another conductor draws twice as tall, and so does a dielectric against another dielectric — but a metal is never drawn to scale against a substrate, because on a real process it would be a hairline — the MMIC stackup above puts 3 µm of metal beside 100 µm of substrate, and the metals are what most of this chapter is about. Where a kind's own range is too wide to draw even on its own, the heights are compressed while staying in order, so a thicker layer still looks thicker; the same MMIC process spans 0.2 µm to 100 µm of dielectric alone, which is 500:1 and would make either the capacitor film a hairline or the substrate four screens tall.

The drawing carries no note about this, deliberately — a caveat printed on every stackup anyone ever looks at is worse than a paragraph here. What it does carry is the real thickness, printed on every layer, which is what you actually need to read off it.

The two boundary conditions are properties of the stack as a whole:

• Top — Open (free space above, the usual case) or Ground.
• Bottom — Ground (the usual case) or Open.

The Stackup tab, field by field

Below is the shipped four-layer FR-4 technology — the one a new workspace can be created against — open in the Technology Editor's Stackup tab. Nine entries: four coppers, three dielectrics between them, and two via entries. It is worth opening yourself alongside this page; everything on it is described below.

The top row: what is above and below, and how to add an entry

The summary row: what the stack adds up to, and what it is made of

The filter box below it narrows the list by entry name, and the count beside it is how many of the nine are showing.

Every entry: kind, name, order

Each entry is a card. The grey word at its left is its kind, fixed when it was added. The box beside it is its name, and the name is not decoration: a via entry names the two conductors it spans by name, and an EM setup names its analysis levels the same way. The three buttons at the right are ↑ and ↓ — the list is ordered top to bottom and that order is z — and ✕, which removes the entry.

A Conductor entry

A Dielectric entry

A dielectric has no drawing layer, and there is no picker for one. It is not drawn: it is a sheet of material spanning the whole problem at its stated thickness.

A Via entry

Via entries are listed as their own group below the ordered ones, under a line saying why: a via is not a layer of the sandwich and has no position in the top-to-bottom order.

Where your port's negative terminal is

Every port in an EM run returns through one plane, and the stackup picks it. Not the panel, not the port label, not per port.

The rule, in order:

1. The ground-designated conductor. Mark a conductor entry as the ground reference in the technology editor. The plane is the top surface of the highest ground-designated conductor that lies below the signal level being simulated.
2. Failing that, the stack's bottom. If no conductor is marked and Bottom = Ground, the plane is taken at the bottom of the stack. The run says so in its notes, and asks you to mark one instead — this fallback places the plane by boundary condition rather than by a real conductor's surface, which is a different height by the thickness of whatever is down there.
3. Failing both, the run is refused. No ground reference and no grounded bottom means no second terminal for any port, and there is nothing to solve.

Four consequences worth having in mind:

• Bottom = Ground is a fallback, not an override. Once step 1 finds a designated conductor, the boundary condition is never consulted: it adds no second plane underneath, and it does not make the chosen plane perfect. A designated ground carries its own σ as a lossy plane whatever Bottom is set to, and switching it to Open changes nothing except that step 2 is no longer available.
• The plane is modelled as laterally infinite. It is the boundary condition the Green's function handles analytically, not a meshed pour — so a ground pour drawn as artwork is not it, and a finite plane's edges are not modelled. A conductor marked as the ground reference is not meshed and cannot also be an analysis level; naming one as a level is refused.
• An intervening metal layer does not become ground just by being underneath. The rule keys on the designation, not on stack position, precisely so that an MMIC's second metal level is not mistaken for a plane. Mark what you mean.
• This is the port's negative terminal for every port type — an edge port at a conductor end, an internal delta gap, or an internal port whose whole purpose is to reach it. It is why an internal port needs a path down to the plane at all.

Which conductors get simulated

A conductor entry that is not the ground reference is a signal conductor, and a signal conductor with artwork on it is an analysis level.

• With one signal conductor, that is the level. Nothing to choose.
• With more than one, the EM setup can name the levels it wants (the analysis-level list); with none named, every signal conductor that actually carries artwork is included.
• Levels are ordered bottom to top, and the lowest one sits on the slab's top surface.

Where a conductor's thickness goes

The full-wave solver has no thickness for metal at all. It models a conductor as a zero-thickness sheet at one height — so the slice of the stack that conductor occupies has to be filled with something, and the stackup does not say what fills a metal layer where no metal is drawn. The answer is that the metal's thickness is given to the dielectric on one side of it, and which side is a per-conductor setting: Metal thickness goes to on the conductor's row in the Stackup tab.

Neither setting moves anything, and the stack height is identical either way — the total is the same number in both cases. All that changes is which neighbour absorbs the vanished thickness, and therefore how high above the ground plane the sheet lands.

"The layer above" is what you want almost everywhere, and it is what a conductor that says nothing means: a trace deposited on a substrate and encapsulated by whatever comes next, whose height above the ground plane comes out as the substrate thickness. It is also the setting the closed-form microstrip models agree with — they model real metal of real thickness and measure their height to the metal's underside.

"The substrate below" is for the lower plate of a capacitor. With the thickness given to the layer above, that plate's whole metal thickness lands inside the plate gap, and the solver separates the two sheets by the capacitor dielectric plus that metal — 3.2 µm rather than 0.2 on a typical MMIC metal. Giving it to the substrate below instead puts the gap back to the dielectric alone. The shipped MMIC technology does exactly this on Metal1.

And it applies only where the capacitor does. A run that is not analysing the plate has no plate gap to get right, so a conductor directly under a patterned dielectric is put back to the default for that run — the same run note that reports the dielectric reports this. That is what lets one technology set it at all: an ordinary line on Metal1 still solves against 100 µm of GaAs, exactly as it did before the capacitor module existed.

The trade is stated rather than hidden: in a capacitor run a Metal1 microstrip's EM substrate is 103 µm of GaAs rather than 100 — a ~3% height shift, against a 16× error in the modelled plate separation. The closed-form microstrip models are unaffected either way; they model real metal of real thickness and measure their height to the metal's underside, so in such a run they and the EM result differ by up to one metal thickness. The run's notes name each level's z and the surface it sits on, which is where you read back what was actually solved.

The slab, and what makes one solvable

The solver works on the dielectric between the ground plane and the lowest analysis level. Two stackup mistakes are refused by name rather than solved around:

• The signal conductor sits at or below the ground plane. There is no slab between them. Almost always a stackup written in the wrong order — the list runs top to bottom.
• There is no dielectric entry between the plane and the conductor. A conductor floating directly on a plane with nothing in between has no substrate to be a microstrip over.

Several dielectric entries between the two are carried as several layers, each at its own thickness, ε_r and tanδ — the medium is stratified and the solver solves it that way. (It used to refuse a stratified region under the feed and tell you to merge the entries into one; merging them changes the physics, and the reason for it is gone.) The run's notes name the layers it found and print the single ε_r it uses to size the calibration standards and the mesh — the series-capacitance equivalent of the stack. That number is a mesh-sizing average and never the reference impedance the answer is published against.

Layers above the top conductor are not part of that slab: the top boundary is what is above, and it is Open unless you say otherwise.

Vias

A via entry is not a layer — it is a connection between two conductor entries, named by name in its Span from / Span to fields. Draw on the drawing layer the entry is bound to, and the EM extractor turns what you drew into a real vertical current path.

Two kinds of artwork count, and both go through the same rules below:

• a via primitive, the pad-and-drill point you place with the Via tool;
• a filled region — a rectangle or a polygon, holes included. This is what a thin-film capacitor's plate connection is: a patch nearly as large as the plate itself, rather than a point. Several regions on one via entry are several footprints of the same connection.

A path on a via layer is ignored, with a note — a path is a centreline and encloses no area, so there is no footprint to mesh. Draw the region instead.

Three rules the extractor applies, each reported when it bites:

• The two conductors must be adjacent in the stack. A via that skips a level is not built, because there is nothing to connect it to in between.
• A via may terminate on the ground plane, and that is the common backside/through-hole case: the named conductor is the ground-designated one, so the via runs from a signal level down to the plane. A via naming some other non-analysis conductor is ignored with a note — it would otherwise silently model a structure you did not draw.
• A via primitive's footprint is squared. A round barrel staircased onto the mesh grid would cost a gridline per facet for no physics, so it is replaced by the equal-area square, which preserves the conducting cross-section. The run reports that it did. A drawn region is not squared — the substitution exists so a circle nobody drew does not staircase, and an outline you drew already is the footprint, so it is meshed as it stands.

A thin-film (MIM) capacitor

A MIM capacitor is a thin dielectric between two metal plates inside the interlayer dielectric. In a stackup it is three entries:

The bottom plate is the interconnect metal underneath — no fourth entry. You draw the two plates and the plate connection; the dielectric is never drawn. A Cap Dielectric or Nitride layer in a layer table is mask documentation, not this.

Both capacitor forms are ordinary multi-level artwork:

• Shunt — bottom plate on the lower metal over one or more backside vias, top plate on the plate metal, feed landing on the upper metal through a plate-via region.
• Series — feed in on the lower metal, which is the bottom plate, and out on the upper metal through the plate via.

The capacitor dielectric rides along only when its plate is analysed

There is one MMIC technology, and it carries the capacitor module. That is only possible because the capacitor dielectric is tied to its plate — the Patterned with setting on its row names MIM Metal, and it means this film exists where that metal's artwork is, and nowhere else, which is what a thin film physically is: deposited under the plate and etched away everywhere around it.

So an EM run carries the film only if the plate is one of its analysis levels. Draw a capacitor and the plate has artwork on it, so the film is there and the plates are 0.2 µm apart. Draw plain interconnect and it is not, so the film enters the medium as air at the same thickness — nothing above it moves — and the lower metal's thickness goes back to the layer above. That run is then identical, number for number, to the same run on a stackup that never had a capacitor module in it. No setting to remember, and nothing to switch.

It is always reported. A run whose tie deactivated says so in its notes, naming the dielectric, the plate that would switch it back on, and the thickness setting it reverted. A medium you did not author and cannot see is exactly the kind of change that produces a complete, believable answer to a question nobody asked.

Why it has to work this way: a stackup dielectric is laterally infinite, so a film that was simply present would be present in every run. That is not free, and both costs are large enough to see:

• Airbridge posts would stop solving. A post between the two metals would cross a dielectric interface, and a via that crosses one is refused by name — the closed-form integral along a via is written in one region's coefficients. That refuses the whole run, it does not drop a shape.
• A line on the lower metal would move. The 0.2 µm ε_r 6.8 sheet would sit on it as superstrate: measured on the acceptance line, ε_eff rises ~1.7% and Z₀ falls ~2.8%.

Both are correct physics for a run that has a capacitor in it, and wrong for one that does not. The tie is what tells the two apart. (circuitRF shipped two MMIC technologies for exactly this reason until the tie existed; if you have a workspace holding its own copy of the older pair, they still work — nothing in a workspace is rewritten by a new release.)

What is still bounded: with the plate level in the analysis, a post between the two interconnect metals skips a level, and a via must span two conductors that are adjacent in the analysis. It is dropped with a note. Capacitor plates and airbridge posts in one EM setup remain separate runs — but they are now separate runs on one technology, not two.

Adding a capacitor module to an imported technology

A technology imported from a process description often arrives without its capacitor module. A process stack description states the interconnect — the metals, the insulation between them, the vias that join them — and treats an optional thin-film module as exactly that: optional, and frequently left out, while the layer table shipped beside it still lists the module's drawing layers. The import is faithful to what it was handed, so what you get is a valid technology whose plate layers draw perfectly and connect to nothing.

The import report says so, by name. Two of its notes are about this and only this:

• "No via in the file names these conductors…" — a conductor the stack describes that no via entry reaches. It cannot be connected, and the file never said how it should be.
• "The layer table defines N drawing layer(s) no stackup entry is bound to…" — layers you can draw on that the stack does not model. A shape on one is artwork, not structure. A real layer table has plenty of these legitimately, so the note counts them and names the first dozen.

Neither is an error, and neither is a guess: nothing in the file states the missing piece, so circuitRF names the gap rather than inventing an entry to fill it.

The fix is three rows in the Technology Editor's Stackup tab, in stack order, and it takes about two minutes. Numbers below are silicon-nitride-class examples — take yours from the process:

Insert them between the two interconnect metals, in that order, top plate above dielectric. The bottom plate is the interconnect metal underneath — there is no fourth row, and nothing is drawn for the dielectric.

ε_r comes from the capacitance density the process quotes, which is the number a process actually publishes:

ε_r = C″·d / ε₀

At C″ = 0.30 fF/µm² over d = 0.2 µm that is 6.8 — the value the shipped MMIC technology carries. Work it out from your own two numbers rather than copying a permittivity out of a materials table: the capacitance is what you want the model to reproduce, and d and ε_r only ever appear together in it.

Then two settings on the rows around it, and neither is optional:

• Tie the dielectric to the plate — Patterned with on the dielectric's own row, set to the top plate you just added. Without it the film is a continuous layer of the medium, present in every run on this technology, and the two costs in the tie's own section land on your interconnect: airbridge posts between those metals refuse the whole run, and a line on either metal moves in ε_eff and Z₀.
• Give the lower metal's thickness to the substrate below — see Where a conductor's thickness goes. A conductor is solved as a zero-thickness sheet, and by default its thickness is given to the layer above it, so the modelled plate separation would be your dielectric plus the lower plate's whole metal thickness — several times the gap you just entered, with a plausible capacitance to show for it. The tie reverts this setting for you in any run that is not analysing the plate, which is why it is safe to set at all.

Add the rows to the technology your designs already use — there is no copy to make and no retargeting to do. With the tie set, a run that draws no plate artwork extracts exactly as it did before you added the rows: the film enters the medium as air at the same thickness and the sheet surface goes back, and the run's notes say so.

What activation does change, stated so it is not a surprise the first time a capacitor run disagrees with an interconnect one: in a run that does analyse the plate, the film is real, and the lower metal's line sees it. Its thickness is given to the substrate instead, so that substrate grows by that metal's own thickness, and ε_eff/Z₀ move with it. That is the capacitor run's real physics, not an artifact — it is the same structure a capacitor sits in.

Two things to know before you read a number off the result: within a run the dielectric is laterally infinite — present everywhere at its stated thickness, which is a good approximation because the fields that set the capacitance are confined under the plates — and the mesh has to resolve the gap, which is the subject of the next section.

Reading a capacitance off a MIM run

The shunt form's backside via sets an upper frequency. A vertical basis carries uniform current along its whole run, so a via is refused above k·ℓ = 0.3. Through 100 µm of GaAs that ceiling is just under 40 GHz; the refusal says so and names the number it computed. The series form has no such via and no such bound.

What the EM engine does not read

Stated plainly, because a field that is carried but unused is worse than one that is absent:

• Conductor thickness reaches the full-wave kernel's loss model but not its GEOMETRY — it still solves a zero-thickness sheet, so t sets the sheet's surface impedance (and therefore its loss) and nothing about where the metal is. The thickness is also used by the cross-section kernel and by interchange, and the full-wave kernel gives it to one of the two dielectrics beside the conductor. Which one is normally invisible (3 µm of metal under a 100 µm substrate moves nothing), and matters exactly once: between the two plates of a thin-film capacitor. It is a per-conductor setting — see Where a conductor's thickness goes.
• A via's fill and wall thickness are carried for thermal work, not read by the RF solve: a plated wall a few µm thick is many skin depths at RF, so plated and solid behave the same.

Checking what it resolved to

Every EM run says which conductor it used as ground, and at what height, in its notes — along with the level list, the slab it built, and any via it ignored or built for you. That report is the authoritative answer to "where is my port's negative terminal", and it is written by the code that actually did it rather than re-derived for display.

If you are chasing a result that looks plausible but wrong, read those notes before anything else: almost every stackup mistake produces a complete, believable answer for a structure you did not draw.

See also: The MoM engine for the ports themselves, EM Setup for the panel that runs them, and The Layout Editor for the rest of the technology file.