Importing a SPICE Model

What circuitRF carries across from a .model card or a .subckt, what it leaves behind, and why — including where to read the list of parameters that did not come with it.

Two ways a SPICE file becomes a circuit

Both start from the same file and use the same translation, so everything on this page applies equally to either.

Route	What you get	Use it when
The SpiceModel component Components › SPICE Model or Subcircuit	A component that runs from the file. Nothing is copied; edit the file and the schematic follows it.	The file is the authority and must stay so.
Copy to Workspace as Cell… (the project tree's context menu)	An editable cell — a schematic you can open, re-symbol and change.	The model is a starting point rather than the last word.

A .model card circuitRF has a device for becomes that device, with its terminals where that device's terminals are. A .subckt becomes a schematic — every element inside it placed as an ordinary component, wired as the definition wires them, with the definition's own port names on the pins.

A packaged part's parasitics are components, not parameters

A vendor file for a real transistor is usually a .subckt: a .model card for the die, wrapped in the lead inductances and package capacitances that dominate its behaviour above a gigahertz or two. Those wrappers come across as ordinary R, L and C instances, because that is what they are. If you import the bare card instead, you get the die and no package — a far larger difference than anything else on this page. Leave Name blank and the highest-level definition is chosen, which is the wrapper.

Nothing is dropped silently

Every parameter on a card that circuitRF does not carry is named, every time:

RF_NPN_DIE   NPN  —  34 parameter(s) — 6 not carried: AF, CJS, KF, MJS, PTF, VJS

Three things about that line are deliberate:

It is exhaustive. The translation walks a table of the parameters circuitRF has a home for; everything the table did not consume goes into the list. A parameter cannot be quietly absorbed, because absorbing it is not one of the outcomes.
The spellings are your file's, not circuitRF's. They are echoed exactly as the card writes them, so you can search for them in the file rather than translating a name back.
It survives the import. For a cell built with Copy to Workspace as Cell… the same list — and the notes below — are written onto the cell's own schematic as a text annotation. Weeks later, the cell still says what it was built from and what did not come with it.

Alongside the not-carried list, the translation reports notes: decisions it made that you could reasonably want to see. Which of two published MESFET laws a card was read as and what said so; that a gate capacitance on the card switched the FET's charge model from a constant capacitance to a bias-dependent junction; that a card's RD/RS were placed as resistors beside the transistor; that a MOS card states no TOX and therefore has no intrinsic gate charge. These are not warnings — they are the reasoning, written down.

Why a parameter is not carried

There are five reasons, and every dropped parameter is one of them.

1. There is no analysis that would read it

KF and AF — the flicker-noise coefficients — appear on every semiconductor card and are carried by none of them. circuitRF has no noise analysis for them to feed. Accepting them would put two rows on the built cell that look honoured and change no result, which is worse than an empty space: a parameter this model does not read is not offered.

2. The device has no node for it

A bipolar card's CJS/VJS/MJS describe the collector–substrate junction. A discrete RF transistor has no substrate terminal to attach one to, and adding a fourth pin would change what the symbol means.

Self-heating is the same shape of omission across every family. The junction temperature is a Temp parameter, not a solved node, so there is no electrothermal feedback and nothing for a card's thermal parameters to connect to. A thermal model belongs around the part.

3. circuitRF's formulation cannot express it

A bipolar card's PTF is excess phase — a delay. circuitRF's weighting functions carry 1 and jω, not exp(−jωτ), so there is no term in the device for a delay to become. The same reasoning retires the MESFET family's transit-time delay.

Also here: subthreshold conduction (NFS) on the MOS cards, because the classical law goes to exactly zero at threshold; quasi-saturation on a VDMOS card, which needs a drift-region model and a second internal node; the level-3 impact-ionisation substrate current; and the Statz/TOM charge formulation, which works on a smoothed effective voltage rather than on Vgs and Vgd separately and is a different scheme rather than a parameter change.

4. It belongs in the schematic, not in the device

A MESFET card's RD and RS are not carried, because circuitRF's MESFET family has no drain or source parasitic resistance of its own. They are not lost either: the import places them as ordinary series resistors beside the transistor and says so in a note.

The same two spellings mean different things on a JFET card

A JFET card's RD and RS are carried, as model parameters — circuitRF's JFET puts them on internal nodes of its own, so the schematic shows one device rather than a transistor with two resistors beside it. The two cards spell them identically and the difference is invisible once the cell is built, which is why the translation states which happened every time.

5. It belongs to a law circuitRF does not implement

A JFET card stating B, ALPHA or VK is stating parameters of a higher published JFET level — a doping-profile knee and that level's own channel-length modulation. There is no square-law parameter that means the same thing, so they are named rather than folded into LAMBDA, which is a different quantity. The card is still read as the square law rather than refused, with a note saying the device will be optimistic where those terms matter.

The MOS rule runs both ways. On a level-1 binding the six short-channel parameters (ETA, THETA, KAPPA, VMAX, DELTA, XJ) are not carried; on a level-3 binding LAMBDA is not, because level 3 computes the output slope from a real shortening of the channel rather than fitting it. Carrying a parameter onto a level that never reads it is the worse failure: it lands on the cell as an ordinary row, looks honoured, and is discovered much later by wondering why changing it does nothing.

A card's LEVEL number is never simply obeyed

On a MESFET card the level numbering is not portable — the same integer selects a different law in different dialects — so which law a card states is decided from its parameters: B appears in the Statz law and in no other, so stating it is the file's own unambiguous answer. LEVEL is listed as not carried so nobody concludes it was honoured.

On a MOS card the classical numbering is portable — 1, 2 and 3 mean the same three published models everywhere — so the number is read, and 4 and above are refused (see below). LEVEL itself is still not carried: it selects a model rather than being one of its parameters.

What each card type leaves behind

Named omissions only — the ones circuitRF has made a decision about. Anything else your card states still appears in the not-carried list by name. The last column links to the device's own physics, where each omission is stated again from the model's side.

Card	Built as	Named omissions	The device
`D`	Junction diode	`KF`/`AF`; `IKF` — the high-injection knee, which this diode has no term for	Diode
`NPN`, `PNP`	Bipolar transistor	`CJS`/`VJS`/`MJS`, `PTF`, `KF`/`AF`	What is modelled
`NMF`, `PMF`	MESFET — Curtice quadratic, or Statz where the card states `B`	`RD`/`RS` (placed as resistors instead), `LEVEL`, `KF`/`AF`; the Statz/TOM charge formulation, transit delay and breakdown	The FET family
`NJF`, `PJF`	Junction FET, square law	`B`, `ALPHA`, `VK`, `KF`/`AF`; gate breakdown and transit-time charge	The junction FET
`NMOS`, `PMOS`	MOS level 1 or level 3, chosen by the card's own `LEVEL`	`LEVEL`, `NFS`, `KF`/`AF`; the six short-channel parameters on level 1, `LAMBDA` on level 3; the level-3 substrate current	The MOS transistor
`VDMOS`	Vertical power MOSFET, n- or p-channel from a bare keyword on the card	Quasi-saturation and subthreshold shaping parameters; flicker noise; self-heating, which for a power device is a real omission	The vertical power MOSFET
`BEAD`	Ferrite bead, four-element equivalent	Saturation — a bead's inductance falls with DC bias current and this is a linear element, so it is not representable at all	Ferrite Bead
`RES`, `R`	Resistor	Everything beyond `R`, `TC1` and `TC2`	—
`CAP`/`C`, `IND`/`L`	Capacitor, inductor	Every temperature coefficient. circuitRF's resistor has `TC1`/`TC2` and its capacitor and inductor do not — which is a real loss of fidelity, and is exactly why it is reported rather than absorbed	—

A p-channel VDMOS is a bare keyword, and a bare negative threshold is not one

A VDMOS card is VDMOS for both channels; a lone pchan keyword is what makes it p-channel. A card with no keyword and a negative VTO looks like a p-channel part — and equally like a (rare, real) depletion-mode n-channel one. Nothing on the card separates them, so it is read as n-channel, which is what the absent keyword means, and the ambiguity is reported rather than guessed at. If it is a p-channel part, build it against the p-channel component instead.

When the whole card is refused

A model type circuitRF has no device for is refused by name — in the parameter dialog the moment the file is chosen, and again at Run. Nothing is approximated. The temptation is real: a JFET's square law looks like the Curtice quadratic with the tanh ignored, and a ferrite bead looks like a parallel RLC. Every one of those produces a cell that simulates and is quantitatively wrong, with nothing anywhere reporting it. Being told costs a minute; a plausible wrong transistor costs the measurement built around it.

Refusals fall into two groups.

circuitRF has no model for this — the refusal names the type and says what is missing, because "unsupported" sends you looking for a setting that does not exist:

An IGBT card. circuitRF has an IGBT, and still cannot take this card: its parameters belong to the ambipolar-transport model and describe the silicon (base width, doping, carrier lifetime), while circuitRF's is an equivalent-circuit model parameterised by what a data sheet gives. Neither set is derivable from the other by renaming.
A controlled-switch card. circuitRF's Switch is an ideal RF block set by its own parameters, not a card-driven behavioural switch.
A MOS card at LEVEL 4 or above. Those are the compact-model families, whose parameters name different quantities under different spellings — almost nothing would be carried, and what came out would be this transistor wearing default numbers.
Any other type, and a card naming no type at all.

In each of those the suggested route is the same: run the model through the VerilogA component, which takes its parameters from the model file itself rather than from a card.

The card does not say enough to build anything — refused for being incomplete, not unsupported:

A BEAD stating only a DC resistance. What could be built is a resistor of a few milliohms, which is not a bead and would simulate perfectly.
A resistor card stating only RSH. A sheet resistance is a resistance per square and needs a width and a length to become a value, neither of which a model card carries.
A CAP or IND card stating no value.

The principle behind all three: a value of zero simulates. Refusing is the only outcome that reaches you.

Working out whether it matters

Ask these in order — most of the time the first one settles it.

Read the value on your own card. A parameter stated as zero was doing nothing in the simulator the card was written for either. A bipolar card very often states CJS = 0 and KF = 0, in which case the substrate junction and the flicker noise are absent from the source model too and nothing at all has been lost.
Put a number on what is left. Most omissions have an arithmetic you can do in a line. Excess phase is the clearest: PTF is the phase in degrees at f = 1/(2π·TF), so a card with TF = 17 ps and PTF = 0.4 is describing 0.4° at 9.2 GHz — below the extraction uncertainty of the package parasitics around it, and not worth a second thought. The same card at PTF = 30 would be a different conversation.
Check you imported the wrapper, not the die. See the note at the top of this page. For a packaged part this is nearly always the largest term.
If the omission is load-bearing, change models rather than parameters. A compiled model through VerilogA takes its parameters from the model file itself, so nothing has to be mapped onto circuitRF's parameter set and nothing is left behind.