Model Composer

A nonlinear FET model, or a passive one, built from measured or simulated data — in a document you can close and pick up again.

What it does

Model Composer builds a model from data. For a transistor it builds a nonlinear FET model, a .cmodel that a schematic places as a ComposedFET and that DC, S-parameters, harmonic balance and loadpull all use. For an N-port it builds a passive model, an ordinary cell of R, L, C and mutuals with the fitted values as its parameters.

The data can be measured (DC and pulsed I–V, multi-bias S-parameters, pulsed S-parameters, large-signal sweeps and loadpull) or simulated (tables of currents, admittances and intrinsic voltages written by another simulator). The work is kept in a .cmc document. It names the data where it lies, records the conditions it was measured under, and holds every setting and every result, so a model can be rebuilt, checked and changed later.

A transistor model has four parts, called constituents: the drain current Id, the gate current Ig (a gate–source and a gate–drain branch), and the gate and drain charges Qg and Qd. Each one is an ANN, a table or an equation. They sit inside an extrinsic network of pads, inductances and resistances. A model can add self-heating, trap states, or a simpler DC/RF dispersion. A .cmodel can also be written without the composer, from equations, a table or a network trained elsewhere: Writing a .cmodel.

Starting from another simulator's design kit? AN-04 — A nonlinear FET model from a reference kit walks the whole flow with block diagrams: which runs to make in the source simulator, the plane to sample at, what each step does with the result, and how to validate against the kit.

The steps

An active document runs through the steps below, in order. Each step's result is stored in the .cmc and stamped with the data and network it came from. When either changes, the step is marked stale.

Fit all (model fit --step all) runs every step the document needs, in this order: the network if any value is free, then thermal, current, traps when a trap model is chosen, charge, and noise when the Noise step lists data. With no S data, the network is held at its values (network: held at its values — no S data to fit to) and the charge step writes the typed capacitances; a fit of the network step alone still refuses.

Data kinds and their conditions

A Touchstone set takes its bias from each file's name or comment lines through a pattern such as Vgs{vgs}_Vds{vds}_Id{id:mA}. The fields are {vgs}, {vds}, {T}, {id}, {ig} and, for a passive family, {geometry}.

Each data set states the conditions it was measured under. Every condition is optional when the set is imported, and the step that needs one names it when it is missing.

Preparing the data

What data a model needs, how to sample it in another simulator, and the file formats each kind is read from — each with an example to copy — are on their own page: Model Data. It covers what a model needs, bias ranges and steps, running another simulator, the file formats, checking a file before importing it and what the import checks.

Reference planes

The composer always models in intrinsic voltages, between the core's own gate, drain and source. Each data set states the plane its voltages were measured at:

The intrinsic voltages come from a DC solve of the extrinsic network carrying the measured currents. Intrinsic points therefore do not lie on a grid, even when the measured ones do. ANNs train on them directly, and tables re-grid them.

A simulated table that also carries intrinsic voltages gets the computed ones checked against them. model deembed reports the largest difference, for example max |ΔV| 3.1e-10 V between its intrinsic voltages and the computed ones.

The six-pin network

The extrinsic network is an ordinary schematic with six numbered pins: 1, 2 and 3 are the extrinsic gate, drain and source, and 4, 5 and 6 are the intrinsic gate, drain and source. Pin 3 is the ground the data is referenced to. Each pin is numbered once. A network that breaks this rule is refused, and nothing is written.

The network's values are its variables. Each one can be locked, bounded, tied to another (rd × 1.2) and fitted. Three stock networks are provided: GaN two-shell (outer pad capacitances, inductances with a gate–drain mutual, inner capacitances, then the series resistances), classic single shell, and series only. The network is fitted cold-FET (a pinched-off and a forward-gate point), multi-bias (the intrinsic capacitances made flat in frequency at every chosen bias), or both. After a fit, each value has a standard error, and a value the data barely determines is marked with the partner it is correlated with.

Methods and their defaults

A model never extrapolates freely. Outside its training domain each constituent is continued linearly from the domain's edge. A current also gains a conductance on its own branch, which grows with distance from the edge: ten times the current's own conductance at the edge it leaves, capped at ten times its largest in the data. Where the data is flat, as a gate current below pinch-off, the continuation stays flat; where it is steep, as the forward gate diode, it stays steep. The Current step reports that conductance at each current's lowest and highest Vgs, as IgGs 2e-09 S at −6 V, 4.9 S at 1 V. The data is still the better answer: keep it wider than the voltages the circuit will reach, because beyond it the current is a continuation, not the device's.

How an ANN is trained

An ANN constituent is a small network, two hidden layers of 8 tanh neurons by default, trained by circuitRF's own trainer. It trains on two kinds of target, alone or together:

The adjoint method for the charges

S-parameters do not measure a charge. They measure its derivatives: at each bias the intrinsic admittance gives the four capacitances C11 = ∂Qg/∂vgs, C12 = ∂Qg/∂vds, C21 = ∂Qd/∂vgs and C22 = ∂Qd/∂vds, averaged over the band where they are flat. An ANN charge is trained on those derivatives alone [P1 §6.3], [X03]:

1. At each bias the network gives its value and its derivatives with respect to its inputs. The derivatives come from a second network carried forward with the first, so they are exact, never differenced.
2. The loss is the weighted squared difference between those derivatives and the measured capacitances. For Qg it is (∂Qg/∂vgs − C11)² + (∂Qg/∂vds − C12)², summed over the biases.
3. The loss's gradient with respect to every weight is back-propagated through both networks at once: the exact adjoint sensitivity of [X03]. An L-BFGS optimiser [NW06] minimises it.
4. Derivatives fix a charge only up to a constant, so an anchor holds each charge at zero at one bias: (0, 0) by default, or the bias you state, moved to the nearest data point when it lies outside the data.

The result is one function per terminal, so the model conserves charge whatever the data. When the measured capacitances are not the derivatives of one function (their curl, which Check (a) reads, is not zero), the fit is the least-squares compromise between them [P1 §6.3.6], and Check (b) reads near zero on the model. A table charge takes the other route and integrates the capacitances along a path, so its result depends on the path [P1 §6.3]; the adjoint-trained ANN has no path.

A bias whose capacitances are not flat across the band weighs less: when the worse of C11's and C22's flatness exceeds FlatnessLimit (0.1), the point weighs (limit/flatness)². With S at two temperatures or more, an ANN charge takes T as a third input, and the anchor holds both charges at zero at every temperature, so heating moves no charge at the anchor bias [X10]. Drift charge in Qg splits the gate charge into depletion charges, fitted the same way to the capacitances near vds = 0, and a drift charge that follows Id [I11].

The currents

Id and Ig train on the measured values, Id weighted relative to the current with a floor (IdFloor). With self-heating, Id also trains on derivatives: the I–V values at each point's junction temperature, and each S point's RF Gm and Gds as ∂Id/∂vgs and ∂Id/∂vds at the same point [X03], [X10]. One function then gives both the DC and the RF output conductance [P1 §6.6]. With the current step's Symmetry set to Exchange in the .cmc, the currents are defined for vds ≥ 0 only, and at negative vds they are their own image with drain and source exchanged [P1 §6.5], [X07]. It is off by default, because a field-plated power device is asymmetric by design.

Common to every ANN

• Each input is scaled onto [−1, 1] over the training points, and the output onto the same range, so one network size suits a 10 mA device and a 10 A one.
• Restarts (3 by default) start from different seeded weights, and the start with the lowest held-out error is kept. The same data, settings and seed give the same model, to the bit, on every machine.
• Held out (10 % by default) are spread across the bias plane rather than taken from one corner, and the status strip's held-out error is the model's error on them.
• Iterations cap the optimiser. It stops sooner when the loss stops falling.
• A network with more weights than a tenth of its targets says so in one line: it can fit the noise.

Charge conservation

The charges are charge functions, so a model is charge-conserving by construction. Its capacitances are derivatives of one charge each, and no DC is ever made by displacement current. Check Charge Conservation checks three things:

Check (a) needs S at 4 biases or more across the bias plane; with fewer it reports not run and the number of biases, which is not a failure. With typed charges it reports not run, as there is no S data. A linear or typed charge's (b) reads zero.

A non-reciprocal capacitance matrix (a transcapacitance, C21 ≠ C12) is reported for information. It is physical, and it is not an error. Checks (b) and (c) also run on any nonlinear device in a netlist: model check-charge design.cnl --device X1 --bias vgs,vds.

Temperature

Data at two or more temperatures makes T an input of every constituent. The model then follows the run's ambient temp, clamped to the data's range with one warning, and self-heating is available. An equation template's current scale (Ipk, Beta or Idss) is then linear in T unless you say otherwise; see the method picker.

Data at one temperature makes a model valid at that temperature, T0, with no temperature dependence. Self-heating is unavailable. A run at another temp prints one warning naming both temperatures and uses the model as it is.

Self-heating needs an Rth. Type it, or extract it from pulsed I–V at two or more chuck temperatures, pulsed from a quiescent point that dissipates nothing, together with DC I–V at the same biases. Extraction trains an isothermal current on the pulses, finds the junction temperature at which it gives each DC point's current, and fits the rise against the dissipated power. The thermal dynamics are a typed Cth, a typed τth, a Foster ladder, or τth fitted to the low-frequency roll-off of Re Y22. That fit is not offered while traps are modelled, because the roll-off holds trap time constants too.

When drain lag is modelled, type Rth (from a thermal simulation, for example) rather than extract it. A pulse from a 0 V drain leaves the trap state short of its DC value, and extraction reads that shortfall as heating.

How traps work in the model

A GaN FET remembers the voltages it has just seen. A high drain voltage or a deep pinch-off captures electrons in traps near the channel, and the charge they hold reduces the current until it is released ([V01], [B02]). Capture is fast and release is slow, and an RF period lies between the two. At RF the current therefore depends on the extreme voltages of the recent past as well as on the voltages now, which a DC I–V cannot show.

The model holds that memory in a small network per trap state. Each network is one internal node, and the node's voltage is the state, in volts.

• A network reads and does not load. It reads the intrinsic vgs or vds, inside the extrinsic network, and draws no current from it. A state reaches the terminals only through the current it changes.
• The two states are independent. Each has its own node and time constants, its own toggle in the Traps step and its own instance switch. A model can have either or both, and with both the current responds to the two at once.
• At DC a state equals its voltage: φ1 = vgs and φ2 = vds. The difference between DC and RF appears only when a voltage moves faster than its state can follow.

The two networks

Figure 2 is the CaptureEmission model ([P1] eqs. 6.73–6.74, [X10] eqs. 1.3–1.4). Each state has a slow path through a resistor and a fast path through a diode. Gate lag and drain lag differ in the voltage they read and in the diode's direction.

These are the model's equations, written as a circuit:

C·dφ1/dt = (vgs − φ1)/R_emit,1 − I_s,1·(e^((φ1 − vgs)/Vc) − 1)     gate lag
C·dφ2/dt = (vds − φ2)/R_emit,2 + I_s,2·(e^((vds − φ2)/Vc) − 1)     drain lag

Above e^20 the exponential continues along its tangent, which only a Newton iterate far from the solution reaches. The elements come from the Traps step's settings:

Only TauCapt, TauEmit, Xref and Vc set the behaviour.

Emission is the resistor. With the diode off, the state relaxes towards its voltage with time constant TauEmit. When a state's activation energy Ea is given, emission follows the device temperature, the junction's when the model self-heats, and capture stays fixed ([N22] eq. 3). T and Tref are in kelvin in this equation, although Tref is set in °C:

1/τ_emit(T) = (1/TauEmit)·(T/Tref)²·e^(−(Ea/k)·(1/T − 1/Tref))

Capture is the diode, and its exponential makes capture fast at first and slow as the gap closes. TauCapt is the time scale at a gap of Xref. It is not the time the state takes to arrive. After a large step in vds with the defaults, the gap between the voltage and the state is:

Each decade of time closes about Vc·ln 10 = 115 mV until emission takes over. Capture spread over many decades is what is measured on real devices ([G19]).

The states are behavioural. They separate the two voltages that set the memory and do not locate the traps in the device.

From a state to the current

A state on its own is only a voltage. The coupling decides what it does to the current ([P1] eq. 6.70, [X10] eqs. 1.1–1.5). Under Trained, Id(vgs, vds, T, φ1, φ2) is fitted with the states as inputs. Under Shift, the trap-free current is evaluated at a gate voltage lowered by ΔV = ShiftDrain·(φ2 − vds) + ShiftGate·(vgs − φ1), which reads the trapped charge as a back gate ([P1] §6.6.4, [P21]). Both terms are positive when a state is held away from its voltage, so gate lag and drain lag add. Traps, and what pulsed data allows gives the detail of each.

Under RF the same networks settle instead of recovering:

Gate and drain swing in antiphase, so vgs − φ1 and φ2 − vds are both at their largest when the channel is on and vds is at its lowest. The trapped charge lowers the current exactly there, which appears as knee walkout and as output power below what the DC I–V predicts. The level of the state follows from a cycle's balance ([P1] eq. 6.75), so at any frequency well above 1/τ_emit it depends on the time constants only through their ratio. A two-tone spacing near 1/τ_emit does depend on the time constants themselves.

How pulsed data reaches the states

A pulse measured before emission has moved the state holds that state at the trap-setting bias, while the terminals sit at the pulse's voltages. Under Trained that gives the fit points away from the DC diagonal, at the same terminal voltages but different states:

The three currents differ, and the differences are what Id learns: the first two rows separate gate lag, and the last two separate drain lag. To separate the two states, the quiescent points must move each voltage on its own. A double pulse sets the state with a pre-pulse and is the clearest way to do this ([S14], [G19]). A pulse that goes beyond its setting was partly captured during the pulse and is handled by the set's TrapState ([X10] eqs. 1.8–1.9).

What each analysis sees

GateLag=false or DrainLag=false on an instance removes that node, and the state then takes its DC value at every instant: Switching parts of the model off.

Further reading

The full citations are under References.

Traps, and what pulsed data allows

Traps are a setting. None is the default. CaptureEmission has a gate-lag state and a drain-lag state, each switched on separately. A state is captured quickly when its voltage moves one way and emits slowly when it moves back. The defaults are 10 ns capture at a 1 V gap and 1 ms emission, and emission can be made thermally activated. Custom lets you write each state's dynamics and DC value yourself. How traps work in the model draws the networks and shows what they do.

The coupling says how the states reach the drain current:

Under Shift a drain-lag state held above vds, or a gate-lag state held below vgs, lowers the current. At any DC bias every state equals its DC value, so the shift is zero and the model's DC is exactly the trap-free current. At RF the states are frozen, which gives gm_RF = (1 − ShiftGate)·gm and gds_RF = gds + ShiftDrain·gm, where gm and gds are the trap-free current's. The step fits each strength from these relations over the active S biases. A strength can be typed and locked, and is then not fitted. The time constants are typed in both couplings. Shift is defined for CaptureEmission; the charges take no trap state under it. With self-heating modelled, gm and gds are read at each point's junction temperature, so heating is not counted as traps. Without self-heating, ShiftDrain includes any thermal part of the DC/RF difference.

A trained trap state is fitted from the trap-setting levels in the pulsed data. The level of a set is its pre-pulse bias for a double pulse, and its quiescent bias otherwise.

A pulsed point toward its setting (pulsed no higher in Vds for drain lag, no lower in Vgs for gate lag) sits at the setting's state exactly, because only slow emission acted. A point beyond it was partly captured during the pulse. The set's TrapState decides what happens to it: auto keeps it for validation only, setting takes the setting's state, and extreme takes the pulse's own voltage as the state.

DC/RF dispersion is the simpler alternative to traps. It fits a second drain current, IdRF, to the RF transconductance and output conductance, and the model follows Id at DC and IdRF above the corner set by τ. Dispersion and traps are not combined, in either coupling.

Periphery scaling

A model records the measured device's finger count N0 and unit gate width W0. Export needs both. An instance's N scales the model:

For the GaN two-shell network the series resistances are perFingerInverse, the inner capacitances perFinger, and the pad capacitances, inductances and mutual fixed. Every rule can be changed per value. m places whole devices in parallel, so m=2 N=8 is two 8-finger devices.

Passive models

A passive document holds one N-port block, or a family of blocks over a geometry value such as the turns of a spiral. Analyse reports the block's reciprocity, passivity, symmetry, low-frequency asymptotes and self-resonances, and fits a rational model. Propose ranks a library of twelve topologies (series and parallel RLC, an inductor with skin effect, capacitor and resistor parasitics, π, T, bond wire, via, spiral, MIM and a line with pads) against the data, or fits a topology you draw. Fit gives each value with its error.

A family is fitted as one law per value, a polynomial or a rational function of the geometry. The middle geometry is held out and predicted, and the result reports its error. Export writes a cell. A single fit's cell takes the fitted values as its parameters, each in the unit that keeps it between 1 and 1000 (nH, fF, Ω). A family cell takes the geometry as its only parameter: the element values stay variables on the cell's schematic, each a law of the geometry — x is the geometry normalised to the fitted range and every law a short polynomial or ratio in it — and the cell warns once when it is placed outside the fitted range.

The example

File ▸ New ▸ Examples ▸ Model Composer opens a workspace with three documents built this way:

• synthetic-gan: a GaN FET built from synthetic DC, pulsed and multi-bias S data, with a fitted network, ANN currents, adjoint-ANN charges, self-heating and drain lag. Its 8-finger model drives a class-AB power sweep and a loadpull.
• passive-spiral: a family of spiral inductors over turns, fitted and placed in a filter at a turn count between two measured ones.
• simulated-tables: a model built from a simulator's tables, showing the intrinsic-voltage cross-check.

The synthetic-gan model is also there as Verilog-A source, gan_4x125.va, and the GanVerilogA bench runs the two side by side: Verilog-A export.

Its README lists every setting it uses, and the value a real job would use where it differs.

Opening a document

Tools ▸ Model Composer… opens a window on a new document and asks one question: Active (a three-terminal FET) or Passive (an N-port). Nothing is written until the first save, which asks where the .cmc goes; choosing a network saves first, because the document's data and network files are found relative to it. Importing data into a new document asks for the data first, then opens the Save dialog in the data's folder with the first file's name filled in, since the data is kept beside the .cmc. Cancelling that Save imports nothing.

A .cmc in a workspace opens on double-click in the project tree, and the window's Open button opens one from anywhere. Each document has one window; opening a document that is already open brings its window forward.

Closing a window with unsaved work asks whether to save it. A document is reopened where it was left: the same panels, the same step, and the same bias cursor.

An opened document needs nothing run to be looked at: its data opens and every step that has a result draws it. The step rail marks each finished step ✓, and the status strip says what is there, e.g. 8 data sets open · done: Pads, Network, Current, Charge, Thermal, Traps, Export. Run re-runs the selected step; on the Data step, with data already imported, it reloads that data, and Import… is on the ▾ and beside the data-set list.

The window

Panel lamps. Each panel has a lamp on the toolbar; a lit lamp means the panel is on screen. Hiding a panel gives its space to the others. The last lit lamp cannot be turned off. Which panels are hidden is saved in the document. The splitters between panels drag in both directions.

The step rail. Active documents have Data · Pads · Network · Current · Charge · Thermal · Traps · Check · Validate · Export; passive ones have Data · Topology · Fit · Export. A step that cannot run yet is dimmed and its tooltip says what it needs. A ✓ marks a step whose result the document holds; a dot instead marks a result computed before the data, the network or the trap model last changed. Check and Validate keep no result in the document, so they are marked once run.

The bias cursor. Vgs, Vds, the ambient temperature and the quiescent point. Each list holds only measured values, so the cursor always sits on a measured bias; with a list focused, the arrow keys step it. The lists sit under the plot tabs, beside the plot they set. Every frequency plot is drawn at the measured point nearest the cursor. A list shows only on the plot tabs that read it: Vgs and Vds on the frequency plots, the bias plane and the Gm, Gds and pulsed slices; T and Q where a step's plot picks a data set by them, which is when the data-set list's selection is not one of that step's sets.

The model sweep. On the tabs that evaluate a fitted model rather than show data at a measured bias — the Current step's Model tabs and the Charge step's C–V tabs — the row under the plot tabs holds start, stop and step for vgs and for vds instead, in volts. A value takes effect on Return or on leaving its box; Escape puts back the one it had. Both are intrinsic, the plane the model is fitted on. One voltage is the x axis and the other steps the curves; the x-axis voltage is drawn at its step or at 101 points, whichever is finer. The sweep starts from the step's data span and keeps what you type for the rest of the session; it is not saved in the document.

Running, progress and Cancel

Run runs the selected step's main task, which its tooltip names; the ▾ beside it lists the step's others. Every run happens off the user interface, which stays responsive: the status strip shows the stage — which network is training, Training Ig, start 2 of 3 — and one progress bar, and Cancel stops it.

• One task runs at a time. Starting another while one runs is refused in the status strip.
• A cancelled task changes nothing: the previous result stays exactly as it was.
• A run that changes results (an import, a fit) saves the document first and reads the result back; an edit made while it ran is kept on top of the result.

The Data step

Import (the database button, or Run) opens the importer:

The right side previews the first lines of the first file — for an array file, each array it holds with its shape — and the first points as they will be read; the line at the bottom is what the import will read, how it read any array not in the documented layout, or why it cannot.

The data-set list shows each set's name, kind, ambient, reference plane, quiescent point (and pre-pulse) and point count, and where its charges read their capacitances: Y, its capacitance table or its circuit set. circuitrf model explain says the same. A capacitance table spelled as the matrix whose C12 is positive at most of its points is warned about, since the matrix convention has C12 = −Cgd: the circuit set was probably meant. Selecting a set points the plots and the cursor's lists at it.

Under the list, an active document shows what its data supports, one row per kind of data in the table of what a model needs: I–V, S or capacitances, cold-FET S, two or more temperatures, pulsed data and large-signal runs. A lit row says what that data gives the model; a dim one says what would light it, in the words the step rail uses for a step that cannot open yet, so the two never disagree.

Moving the cursor. On the bias plane, with the lasso lamp off, click a point: it turns green, the Vgs and Vds lists move to its bias, and the other tabs follow. A plot you have zoomed or panned keeps its window while the cursor moves; choosing another tab frames that tab's data. A point of another data set selects that set.

Excluding points. On the bias plane, light the lasso lamp under the plot tabs, choose a reason, then click a point or drag a lasso around several. Points already excluded are included again. Choose Valid instead to make every point the click or lasso takes valid again, excluded or not. Each click or lasso is one undo step.