Footprints

How a part on the schematic gets real artwork: SMT case sizes, IPC-7351B density levels, the land pattern circuitRF generates for each, and what reaches the board.

A footprint is a layout view of a cell

There is no second kind of artifact here, no footprint library file and no registry to keep in step. A footprint is a layout view of a cell — the same .clay the Layout Editor edits and the same view an instance of any other cell resolves to. That one rule is why an imported part shows up beside a built-in case size in the same picker with no extra step, and why a footprint you drew by hand is a first-class choice rather than a workaround.

A component's Footprint parameter names one of three things:

What you point at	Written as	Where the artwork comes from
A built-in case size	`smt:0402@N`	Generated on demand from the case table — it is not a file, and nothing ships a `.clay` per case
A cell in this workspace	a relative path, e.g. `parts/Widget9`	That cell's own layout view, including every part `import part` has ever written here
Your own `.clay`	a relative path to the file	Exactly the artwork in it

Anything that does not begin with smt: is a path, resolved against the document's own folder the same way a cell reference is. There is no third case to learn.

A built-in pattern is generated, not shipped

A stored .clay carries absolute layer keys, and the shipped technologies disagree about every one of them — the same key that is Silk Top on the 2-layer stackup is Soldermask Top on the 4-layer one. A shipped 0402 file would therefore put its silkscreen into a mask opening on the wrong board and nothing would say so. A generated pattern resolves its layers by role against whichever technology is in force, which is the only form that survives contact with more than one board.

Choosing one on a component

Open a component's parameter editor (double-click its body on the schematic). The Footprint row is the last row, laid out like any other parameter: the picker in the value column, the density beside it where a unit would go, and the checkbox in the display column.

Control	What it does
Footprint picker	None, then every built-in case size, then every layout view of every cell in this workspace, then Custom… — which opens a file picker over `.clay`. One list; there is no separate place to look for an imported part.
Density	`M` / `N` / `L` for a built-in case, greyed out for anything else — an imported cell's density is whatever its author drew. See below.
The checkbox	Draws the footprint's case code on the schematic as a third label, after the parameters. Off by default, and nothing is drawn when the footprint is None whatever it says.

The label reads 0402, not smt:0402@N. The reference is machine spelling; a drawing gets the case code, or a cell's folder name, or a custom file's name without its extension.

The list is filtered by port count

A row is offered only when its pad count equals the component's port count, so the built-in case sizes — which are all two-pad — do not appear at all on a four-port part, and a nine-pad cell you imported appears only on a nine-port one. Offering the rest would be offering a refusal: the pad-count contract would report it at Update Layout and place nothing, which is a worse way to learn it.

A freshly placed R, C or L already has one

Place a resistor, capacitor, inductor or one of the two-element RL/RC/LC parts on a design whose technology is a board, and it lands carrying smt:0201@N — the smallest size a person still places by hand. Everything else lands with None: a three-element branch, a PCell, an SnP, a source, a port and a placed cell are all things where guessing artwork would be putting a package on a model.

It is applied at placement and never again. Change the workspace technology later and your parts keep the footprints they were authored with — a default that followed the technology around would be a design that changes when you open it somewhere else.

The simulator never sees it. Footprint is artwork, not a value: smt:0402@N is not an expression, and it is dropped before parameters are resolved, for every component kind alike. It is written into the .cnl — so a headless Update Layout can still read it — and the engine ignores it.

The case sizes circuitRF generates

Two-terminal chips, reverse-geometry chips, larger MLCC bodies, moulded tantalums, two-pad SMD crystals and a wire jumper. The body dimensions read along the termination axis first — the direction the two lands are separated in — so a reverse-geometry row's first number is its short side, which is exactly how the generator uses it.

A crystal's code carries an XTAL prefix (XTAL3216, XTAL2016) because 3.2 × 1.6 mm is also imperial 1206 — the same body, two land patterns that are not alike. A wire jumper has no body at all: JUMPER2.6 names the pad pitch, and that pitch is what the row's first dimension column reads.

Case	Metric twin	Body	Termination	Family
008004	0201	0.25 x 0.125 mm	0.06 mm	chip
01005	0402	0.40 x 0.20 mm	0.10 mm	chip
0201	0603	0.60 x 0.30 mm	0.15 mm	chip
0402	1005	1.00 x 0.50 mm	0.25 mm	chip
0603	1608	1.60 x 0.80 mm	0.35 mm	chip
0805	2012	2.00 x 1.25 mm	0.40 mm	chip
1206	3216	3.20 x 1.60 mm	0.50 mm	chip
1210	3225	3.20 x 2.50 mm	0.50 mm	chip
1812	4532	4.50 x 3.20 mm	0.60 mm	chip
1825	4564	4.50 x 6.40 mm	0.60 mm	chip
2010	5025	5.00 x 2.50 mm	0.60 mm	chip
2512	6332	6.30 x 3.20 mm	0.60 mm	chip
0306	0816	0.80 x 1.60 mm	0.20 mm	reverse geometry
0508	1220	1.25 x 2.00 mm	0.30 mm	reverse geometry
0612	1632	1.60 x 3.20 mm	0.35 mm	reverse geometry
1808	4520	4.50 x 2.00 mm	0.60 mm	MLCC body
2220	5750	5.70 x 5.00 mm	0.65 mm	MLCC body
2225	5763	5.70 x 6.30 mm	0.65 mm	MLCC body
3216-18	A (EIA)	3.20 x 1.60 x 1.80 mm	0.80 mm	moulded tantalum
3528-21	B (EIA)	3.50 x 2.80 x 2.10 mm	0.80 mm	moulded tantalum
6032-28	C (EIA)	6.00 x 3.20 x 2.80 mm	1.30 mm	moulded tantalum
7343-31	D (EIA)	7.30 x 4.30 x 3.10 mm	1.30 mm	moulded tantalum
7343-43	X (EIA)	7.30 x 4.30 x 4.30 mm	1.30 mm	moulded tantalum
XTAL3216	3216	3.20 x 1.60 mm	1.10 mm	crystal
XTAL2016	2016	2.00 x 1.60 mm	0.70 mm	crystal
JUMPER2.6	wire link	2.60 mm pitch	1.00 mm	wire jumper

0201 imperial and 0201 metric are two different parts

Imperial 0201 is 0.60 × 0.30 mm. Metric 0201 is 0.25 × 0.125 mm, which is imperial 008004 — a factor of 2.4, and both codes are real. Nothing about the mistake announces itself: it places, it renders, it exports, and the first sign of trouble is a board. That is why every case row in every picker, tooltip and message reads its metric twin and its millimetres, and why a bare four-digit token arriving from a BOM is reported as ambiguous rather than guessed.

The three density levels

IPC-7351B states the same land pattern at three land protrusions, and the density picker chooses between them. The part is identical in all three; what changes is how far the copper reaches past it.

One case, 0805, at the three IPC-7351B density levels. The part is the same in all three; what the level sets is how far the land reaches past it — 0.55 mm of toe at M, 0.35 mm at N and 0.15 mm at L.

Level	Written	For
M — most	`smt:0805@M`	Wave solder, hand rework, high reliability. The largest fillet, the largest courtyard.
N — nominal	`smt:0805@N`, or `smt:0805`	General commercial reflow. The default, and what an omitted `@` means.
L — least	`smt:0805@L`	High density, fine pitch. The land barely clears the termination.

One case at two densities is two different cells, not one cell with a setting — which is why a stored reference spells the density out, and why re-pointing a part from @N to @L is the same kind of edit as re-pointing it from 0402 to 0603.

Chips below 1.6 mm get their own goals. IPC splits the table at metric 1608 (imperial 0603) and gives the smaller bodies much reduced fillet goals; circuitRF follows that split, and scales the heel, side and courtyard figures with the toe at that size. Without it an 008004 would be handed a 0.35 mm toe on a 0.25 mm body — a land pattern almost four times the part, which places, renders, exports and is wrong.

What gets drawn, and on which layers

Four generated land patterns at the nominal density, all at one scale: 0402, 0805, 1206 and the 3216-18 moulded tantalum. Copper lands, their soldermask openings, the two silkscreen lines and the courtyard rectangle, on the shipped 2-layer PCB technology.

A generated pattern is four things, each resolved to a layer by role — the technology's F.Cu / F.Mask / F.SilkS / F.CrtYd interchange alias first, then a layer's stated purpose, then its name:

Role	What is drawn	If the technology declares no such layer
Copper	Two lands, each carrying its pin (`1`, `2`)	Refused. There is no land pattern without lands, and the reason is reported by name.
Soldermask	One opening per land, grown 50 µm per side	Omitted, with a note
Silkscreen	Two lines running the length of the body, clear of the mask openings	Omitted, with a note
Courtyard / assembly	The keepout rectangle around the lands or the body, whichever is larger	Omitted, with a note

A missing layer is never replaced by a different one

A silkscreen outline drawn on Soldermask Top because the technology has no silk is worse than no outline at all: the mask layer is manufacturing data, and a stray rectangle in it is a defect nobody sees until fabrication. The same goes for the courtyard, which is never drawn on the board outline — a courtyard rectangle on Edge.Cuts is a routed slot. Every shipped board technology declares Courtyard Top (F.CrtYd); a technology that does not — one you wrote, or one imported from a Gerber set — omits the courtyard and says so in Messages, at Info rather than Warning, because a courtyard is placement metadata that never reaches the fabricated board. A missing soldermask or silkscreen is a warning, because both do.

A pattern is centred on its body, not on pin 1. That is the opposite of the convention the microstrip PCells follow, and it is deliberate: every board format places a part by its body centre, so an imported cell's origin is already there, and one picker listing both would otherwise make a part jump when you changed its footprint.

The origin of the numbers. Spans and gaps are computed from the case's worst-case material condition plus the level's fillet goals, in exact decimal millimetres, and converted to DBU once — so the same case lands on the same DBU on every machine. IPC's statistical fabrication-and-placement allowance is not applied: it needs the board's fabrication tolerance and the assembler's placement accuracy, and a technology declares neither. What you get is the geometric land pattern.

A chip land pattern needs a board

The copper role must be a surface a part can be soldered to — a conductor sitting directly on a solid dielectric. A MMIC technology whose topmost metal is an air-bridge level is refused by name rather than quietly given an 0402 on a GaAs die. This is also the test behind the 0201 default: a default is offered exactly where a land pattern can be generated.

Onto the board

Design ▸ Update Layout from Schematic (⌘U) is what turns the stated footprint into placed artwork. A stated footprint is consulted first, ahead of the kit / cell-reference / PCell chain, because it is an explicit choice somebody made.

Re-pointing updates in place. Change a part from 0402 to 0603, run it again, and the existing instance moves to the new cell and is reported. It does not add a second one.
Setting a footprint back to None removes the artwork, and says so. Leaving it behind would mean the layout says a part is there and the schematic says it is not.
Pads must equal ports. A footprint with two pads under a four-port part is reported and nothing is placed — S4P1 states footprint 0402, which has 2 pads, and the component has 4 ports. Artwork on the board with the wrong pad count is artwork somebody routes to.
Each placement draws its reference designator on silkscreen, taken from the schematic instance name. It is derived, not stored, so a rename in the schematic arrives with the next update and a board can never disagree with the drawing about what a part is called.

An SnP with a reference pin has one more port than its file

A 2-port S2P with External reference pin ticked is a three-port component, and it does not fit a two-pad chip land. This is the pad-count refusal people meet first, and the message names both numbers.

Everything else about Update Layout — packing, the ratsnest, what is skipped and what is reported — is unchanged and is described in Schematic ⇄ layout.

In the layout editor

Two gestures, and they are different things:

Gesture	Where	What it does
Place one by hand	The Footprint… button on the toolbar, beside Instance…	Arms the placement ghost with a land pattern, so you can drop an 0402 onto existing copper with no schematic anywhere.
Re-point what is selected	The Footprint row in the Properties inspector, with its own density picker	Swaps the selected instance's artwork, as one undoable command like any other instance edit.

A part placed by hand corresponds to no schematic component, so it carries no schematic id — and it is given no invented one. It takes its designator from Designator in the same inspector, where you can also hide it, drag its label and Reset the label back to its automatic position above the body.

Neither gesture writes back to the schematic. Re-pointing artwork in the layout makes the two views disagree, which is what Update Layout exists to reconcile and what its change report exists to say. A silent write-back would make an artwork edit change a simulation.

Imported parts, BOMs and part libraries

An imported part is already in the picker. import part — and File ▸ Import ▸ Component… — writes a cell folder holding a symbol plus one or more land patterns as sibling layout views. Because a footprint is a layout view of a cell, that part appears in the workspace section of every footprint picker with no second import and no registration. Density variants an import wrote (-M, -L) are listed as what they are, and a view that is not its cell's primary is listed as that — an instance draws the primary, so choosing one says so in its tooltip and Update Layout repeats it rather than placing the wrong artwork.
A BOM's footprint column is read and reported, never applied. SM/C_0402, C0402, CAP-0402-X7R and 0402 all reduce to the same case; a token that reduces to nothing is shown exactly as written rather than snapped to the nearest code, and a bare token that names a real case in both schemes is reported as ambiguous with both readings named. A column that silently set artwork would be the same class of error as the ambiguity itself.
A railRF part library (.crlib) has a footprint column that is a picker over the same case table, and it stores the scheme (smt:0402) because a bare token is ambiguous. It stores no density: an IPC level belongs to a land pattern, not to a package.
Exports carry it. File ▸ Export ▸ Bill of materials… writes one row per placement with its reference, value and footprint; a board export writes each placement's designator as its reference.

Asking about footprints headless

Two verbs answer without opening anything — see the CLI chapter for the full output:

circuitrf explain Board1/schematic/Board1.csch --footprints
circuitrf check Board1

explain --footprints prints, per component, what it states, what that resolved to, how it got there, and pads against ports on one line with MISMATCH where they differ. check reports a footprint that no longer resolves and a pad/port disagreement as warnings, on the design as a whole.

What this is not

Not a footprint editor. A land pattern is a .clay, and the layout editor already edits those. Custom… means point at one, never draw one here.
Not a parts database. The picker lists case sizes and the cells already in your workspace. It knows nothing about part numbers, manufacturers, stock, or a vendor's recommended pattern.
Not multi-pin packages. Every built-in is two-pad. A QFN, a SOIC or a four-pad crystal is a different land-pattern problem; import one, or draw it, and it is a first-class choice in the same picker.
No parameter handles. A case size is a discrete choice from a table, not a dimension to drag — a grip would let you pull an 0402 into a shape no case code names, and the stored reference would then lie about what the artwork is.
Not a connectivity check, and not a router. Nothing here reads a net, and Update Layout places parts without routing them. Checking that the artwork implements the schematic is LVS, which is a separate command you run when there is copper to compare.