circuitRF Quick Start

circuitRF Quick Start

For engineers who already know circuit simulators. In a couple of pages: what circuitRF is, how it's organized, and how to run a simulation and see a plot.

What circuitRF is

circuitRF is a lightweight, cross-platform RF circuit simulator. If you've used a SPICE tool or a commercial RF/microwave EDA suite, you'll be at home — but the analyses and the workflow are built around the RF problem, not the time-domain transient problem. It is deliberately not a SPICE simulator.

Simulations available:

Data Display: results plot on rectangular, Smith, and polar charts, and in tables. Measured data (Touchstone, .spl, .lpcwave) overlays simulated data on the same axes — a measured loadpull contour plots exactly like a simulated one.

Results are Python-native

Every run writes its results as a NumPy .npy dataset (a named bundle of labeled, unit-bearing arrays — the DataSet/DataCube model). You can plot it in circuitRF or load it straight into Python/MATLAB. Export to .mat, Touchstone, .spl, and .lpcwave is built in.

How a project is organized

circuitRF is a hierarchical, cell-based tool (like the commercial RF suites, not like a flat SPICE deck). The pieces:

No project? No problem

You don't have to build a cell library to try something. Use File → New Schematic to open a standalone schematic — a scratch sheet you can wire up and simulate immediately, with no workspace or cell structure. Save it into a workspace later if it's worth keeping.

The workspace window

A workspace is a folder holding a .cws file and a folder per cell — membership is the filesystem, so the Project panel is showing you what is on disk. Open one and you get the window below: documents in tabs down the middle, tool panels docked around them.

Amplifier Design — circuitRF File Edit Design Simulate Tools View Window Help Amplifier Design FET Amplifier Mitred Bend PCB 2-Layer.ctech Workspace Component Angelov Q1 Type label Instance name Ipk 0.1 A Vpk -1 V P1 1 P2 0 P3 0 Alpha 2 Lambda 0 Cgs 1 pF Cgd 0 pF CapModel 1 Help Properties Analyses Properties + − + − Vdc V1 Vdc = VGS V I IProbe IGS + − Term Term1 Num = 1 Z = 50 Ω C C1 C = 1 mF L L1 L = 1 mH Angelov Q1 Ipk = 0.1 A Vpk = -1 V P1 = 1 Alpha = 2 VAR VAR VAR1 VGS = -2 VDS = 48 I IProbe IDS C C2 C = 1 mF L L2 L = 1 mH + − Vdc V2 Vdc = VDS V + − Term Term2 Num = 2 Z = 50 Ω Welcome Mitred Bend.clay FET Amplifier.csch Opened workspace 'Amplifier Design'. Opened schematic 'FET Amplifier'. Opened layout 'Mitred Bend'. Messages DRC LVS Messages All Search… R GND L M M C NonlinearC + − Term + − TermG VAR VAR MEAS I IProbe V VProbe + − Vdc P1Tone ITone + − VTone 1 2 S2P G L WSProbe 1 2 3 S3P 1 2 SPICE Library Amplifier Design — circuitRF File Edit Design Simulate Tools View Window Help Amplifier Design FET Amplifier Mitred Bend PCB 2-Layer.ctech Workspace Layout Select a shape or instance to inspect. Properties Analyses Properties EM Layer: Bottom Copper Technology: PCB 2-Layer Unit: mil Snap: 1 mil Shapes: 4 Instances: 0 Extent: 11.811 × 10.6299 mil X: — Y: — -6 -4 -2 0 2 4 6 8 10 12 14 16 -4 -2 0 2 4 6 8 Welcome FET Amplifier.csch Mitred Bend.clay Opened workspace 'Amplifier Design'. Opened schematic 'FET Amplifier'. Opened layout 'Mitred Bend'. Messages DRC LVS Messages All Search… R GND L M M C NonlinearC + − Term + − TermG VAR VAR MEAS I IProbe V VProbe + − Vdc P1Tone ITone + − VTone 1 2 S2P G L WSProbe 1 2 3 S3P 1 2 SPICE Library
The workspace window: a schematic open in the document area, the Project, Properties, Library and Messages panels around it, and a layout waiting in the second tab.

Everything in it is movable. Drag a tab to reorder it, against an edge to split the area, or clear of the window to float it; drag a tool panel by its tab to re-dock it anywhere. View ▸ Hide Dockers (Ctrl/⌘+Shift+H) gives the whole window to the documents and back again, and View ▸ Reset Layout restores the arrangement you chose in Settings. The arrangement is saved into the .cws, so a workspace reopens the way you left it.

Region by region, panel by panel: The Workspace.

Build a schematic: components, wires, the pin grid

circuitRF — FET S-Parameters + − + − Vdc V1 Vdc = VGS V I IProbe IGS + − Term Term1 Num = 1 Z = 50 Ω C C1 C = 1 mF L L1 L = 1 mH Angelov Q1 Ipk = 0.1 A Vpk = -1 V P1 = 1 Alpha = 2 VAR VAR VAR1 VGS = -2 VDS = 48 I IProbe IDS C C2 C = 1 mF L L2 L = 1 mH + − Vdc V2 Vdc = VDS V + − Term Term2 Num = 2 Z = 50 Ω circuitRF — FET S-Parameters + − + − Vdc V1 Vdc = VGS V I IProbe IGS + − Term Term1 Num = 1 Z = 50 Ω C C1 C = 1 mF L L1 L = 1 mH Angelov Q1 Ipk = 0.1 A Vpk = -1 V P1 = 1 Alpha = 2 VAR VAR VAR1 VGS = -2 VDS = 48 I IProbe IDS C C2 C = 1 mF L L2 L = 1 mH + − Vdc V2 Vdc = VDS V + − Term Term2 Num = 2 Z = 50 Ω
The schematic editor with the shipped FET S-parameter test bench open.

The short version is below. The editor in full — the Library Palette, every toolbar button, the context menu, and setting up the analysis that runs the circuit — is The Schematic Editor.

  1. Place a component. Click a tile in the Library Palette (or drag it onto the canvas). A ghost follows the cursor; click to drop. The tool stays armed so you can place several. Press R to rotate the ghost, Esc to stop placing.
  2. Wire it up. Press W (or the Wire button) and click from one pin to another. Enter or double-click finishes a wire; Esc cancels it.
  3. Edit a value. Double-click a component's value label right on the schematic to edit it inline — type 50 Ω, 1.2 nH, 2 GHz and press Enter. (Double-clicking the body opens the full parameter editor.)
The pin grid

Connections are exact, not fuzzy. Every component pin, wire vertex, and junction lands on the connection grid (the coarse grid), and two things are connected only when they sit on the same grid point. A separate, finer authoring grid positions labels and annotations. Keep pins on the connection grid and wiring "just works"; a red marker flags an unconnected pin.

Pins vs. Ports vs. Terms

Three things sound similar but do different jobs. The distinction matters because it controls what becomes an external interface versus an excitation/measurement point:

ConceptWhat it isWhen you use it
Pin An interface terminal of a cell. Pins on a cell's symbol are how the cell connects to the parent schematic that instances it. Connectivity only — no electrical model. Inside a cell you intend to reuse hierarchically, to expose its connection points.
Term An S-parameter port termination — a numbered reference-impedance port (default 50 Ω). Each Term carries a Num (port index). On a test bench, to define the ports an S-parameter analysis measures between.
Port The general term for an external connection point. In a cell a port is realized by a Pin; in an S-parameter test bench a port is realized by a Term. Conceptually — "this circuit is a 2-port." How you realize it depends on the context above.
Pin A cell's own connection point. Lives on the cell's symbol, carries no electrical model — pure connectivity. Use it to expose a reusable cell's connections to its parent. + − Term A numbered S-parameter port termination, 50 Ω by default. The point an S-parameter analysis injects a wave and measures the scattered result. Pin A cell's own connection point. Lives on the cell's symbol, carries no electrical model — pure connectivity. Use it to expose a reusable cell's connections to its parent. + − Term A numbered S-parameter port termination, 50 Ω by default. The point an S-parameter analysis injects a wave and measures the scattered result.
The two symbols that realise a port: Pin, a cell's connectivity-only interface terminal, and Term, a numbered S-parameter port termination.

The Reference Guide has a fuller treatment with diagrams; for Quick Start: use Term to define S-parameter ports on a test bench, and Pin to expose a reusable cell's connections.

Run a simulation

  1. Open Simulate → Setup Analyses… (or the Analyses panel) and add an analysis (e.g. S-Parameter, 1–10 GHz). For an HB example, add Harmonic Balance and drive the input with a P1Tone (available-power) source.
  2. Press Run ▶. circuitRF extracts a netlist from the schematic, elaborates it, and runs the analysis on a background thread.
  3. The run writes results/<name>/run.npy. Open Data Displays that are already showing this result refresh automatically.

See the result on the Data Display

  1. Open a Data Display (Ctrl/⌘+Shift+D) and add a plot — Rectangular, Smith, Polar, or Table.
  2. In the trace card, pick the data source (your run), then the signal — e.g. S(2,1). On a rectangular plot choose a transform such as dB20; on a Smith chart the complex value plots directly.
  3. For loadpull, choose the loadpull run and a contour metric (Pout, PAE). The optimum (max-power / max-efficiency) markers and interactive markers read values off the contour surface.
circuitRF - Data Display SParameters circuitRF 2 4 6 8 10 2 4 6 8 10 12 freq (GHz) SP1.S(2,1) dB20 circuitRF - Data Display SParameters circuitRF 2 4 6 8 10 2 4 6 8 10 12 freq (GHz) SP1.S(2,1) dB20
A rectangular plot of the shipped FET test bench's S-parameters, 1-10 GHz.

Headless / command line

The engine runs without the GUI — useful for scripting and batch sweeps. From a .cnl netlist (a human-readable circuit description):

$ circuitrf sparam mycircuit.cnl --freq 1GHz:3GHz:50MHz -o mycircuit.s2p

This reads the netlist, runs the S-parameter analysis, and writes a Touchstone file. (Make sure the circuit's port count matches the extension, or omit -o to let circuitRF name it .sNp automatically.)

Every analysis runs this way, not just S-parameters — dc, hb (harmonic balance), lp and lpp (loadpull and pursuit), and em, which runs an EM setup and writes the same files the Simulate button writes. Results go to stdout and progress to stderr, so a long run can be piped and watched at the same time. The full reference is The Command Line.

Next

Ready to draw something for real? The Schematic Editor covers placing, wiring and analysis setup in full, and Simulations covers every analysis type. New to circuit simulators in general? The New User's Guide starts from first principles. Need exact parameters, algorithms, or the netlist format? See the Reference Guide.